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Yoshinobu Higami: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Yoshinobu Higami, Kewal K. Saluja, Hiroshi Takahashi, Shin-ya Kobayashi, Yuzo Takamatsu
    Compaction of pass/fail-based diagnostic test vectors for combinational and sequential circuits. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:659-664 [Conf]
  2. Yoshinobu Higami, Yuzo Takamatsu, Kewal K. Saluja, Kozo Kinoshita
    Fault models and test generation for IDDQ testing: embedded tutorial. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2000, pp:509-514 [Conf]
  3. Yoshinobu Higami, Seiji Kajihara, Kozo Kinoshita
    Test sequence compaction by reduced scan shift and retiming. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1995, pp:169-175 [Conf]
  4. Yoshinobu Higami, Seiji Kajihara, Kozo Kinoshita
    Partially Parallel Scan Chain for Test Length Reduction by Using Retiming Technique. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1996, pp:94-99 [Conf]
  5. Yoshinobu Higami, Seiji Kajihara, Shin-ya Kobayashi, Yuzo Takamatsu
    Techniques for Finding Xs in Test Sequences for Sequential Circuits and Applications to Test Length/Power Reduction. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2004, pp:46-49 [Conf]
  6. Yoshinobu Higami, Shin-ya Kobayashi, Yuzo Takamatsu
    A Method to Reduce Power Dissipation during Test for Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2002, pp:326-331 [Conf]
  7. Yoshinobu Higami, Kewal K. Saluja, Kozo Kinoshita
    Observation Time Reduction for IDDQ Testing of Briding Faults in Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1998, pp:312-317 [Conf]
  8. Yoshinobu Higami, Yuzo Takamatsu, Kozo Kinoshita
    Test sequence compaction for sequential circuits with reset states. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2000, pp:165-170 [Conf]
  9. Yoshinobu Higami, Yuzo Takamatsu, Kewal K. Saluja, Kozo Kinoshita
    Fault Simulation Techniques to Reduce IDDQ Measurement Vectors for Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1999, pp:141-146 [Conf]
  10. Yoshinobu Higami, Naoko Takahashi, Yuzo Takamatsu
    Test Generation for Double Stuck-at Faults. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2001, pp:71-75 [Conf]
  11. Yuichi Sato, Hiroshi Takahashi, Yoshinobu Higami, Yuzo Takamatsu
    Failure Analysis of Open Faults by Using Detecting/Un-detecting Information on Tests. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2004, pp:222-227 [Conf]
  12. Hiroshi Takahashi, Marong Phadoongsidhi, Yoshinobu Higami, Kewal K. Saluja, Yuzo Takamatsu
    Simulation-Based Diagnosis for Crosstalk Faults in Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2001, pp:63-0 [Conf]
  13. Hiroshi Takahashi, Yukihiro Yamamoto, Yoshinobu Higami, Yuzo Takamatsu
    Enhancing BIST Based Single/Multiple Stuck-at Fault Diagnosis by Ambiguous Test Set. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2004, pp:216-221 [Conf]
  14. Yoshinobu Higami, Shin-ya Kobayashi, Yuzo Takamatsu
    Modifying Test Vectors for Reducing Power Dissipation in CMOS Circuits. [Citation Graph (0, 0)][DBLP]
    DELTA, 2002, pp:431-433 [Conf]
  15. Hiroshi Takahashi, Shuhei Kadoyama, Yoshinobu Higami, Yuzo Takamatsu, Koji Yamazaki, Takashi Aikyo, Yasuo Sato
    Effective Post-BIST Fault Diagnosis for Multiple Faults. [Citation Graph (0, 0)][DBLP]
    DFT, 2006, pp:401-109 [Conf]
  16. Yoshinobu Higami, Shin-ya Kobayashi, Yuzo Takamatsu, Seiji Kajihara, Irith Pomeranz
    A Method to Find Don't Care Values in Test Sequences for Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    ICCD, 2003, pp:397-0 [Conf]
  17. T. Seiyama, Hiroshi Takahashi, Yoshinobu Higami, Kazuo Yamazaki, Yuzo Takamatsu
    On the fault diagnosis in the presence of unknown fault models using pass/fail information. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2987-2990 [Conf]
  18. Yoshinobu Higami, Seiji Kajihara, Kozo Kinoshita
    Reduced Scan Shift: A New Testing Method for Sequential Circuit. [Citation Graph (0, 0)][DBLP]
    ITC, 1994, pp:624-630 [Conf]
  19. Yoshinobu Higami, Kewal K. Saluja, Kozo Kinoshita
    Efficient Techniques for Reducing IDDQ Observation Time for Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1999, pp:72-77 [Conf]
  20. Yoshinobu Higami, Kewal K. Saluja, Hiroshi Takahashi, Yuzo Takamatsu
    Fault Coverage and Fault Efficiency of Transistor Shorts using Gate-Level Simulation and Test Generation. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2007, pp:781-786 [Conf]
  21. Yoshinobu Higami, Seiji Kajihara, Hideyuki Ichihara, Yuzo Takamatsu
    Test cost reduction for logic circuits: Reduction of test data volume and test application time. [Citation Graph (0, 0)][DBLP]
    Systems and Computers in Japan, 2005, v:36, n:6, pp:69-83 [Journal]
  22. Yoshinobu Higami, Kewal K. Saluja, Yuzo Takamatsu, Kozo Kinoshita
    Static test compaction for IDDQ testing of bridging faults in sequential circuits. [Citation Graph (0, 0)][DBLP]
    Systems and Computers in Japan, 2000, v:31, n:11, pp:41-50 [Journal]

  23. New Class of Tests for Open Faults with Considering Adjacent Lines. [Citation Graph (, )][DBLP]


  24. Design of partially parallel scan chain. [Citation Graph (, )][DBLP]


  25. Test Generation and Diagnostic Test Generation for Open Faults with Considering Adjacent Lines. [Citation Graph (, )][DBLP]


  26. Timing-Aware Diagnosis for Small Delay Defects. [Citation Graph (, )][DBLP]


  27. A Novel Approach for Improving the Quality of Open Fault Diagnosis. [Citation Graph (, )][DBLP]


  28. Fault Effect of Open Faults Considering Adjacent Signal Lines in a 90 nm IC. [Citation Graph (, )][DBLP]


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