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Pallab Dasgupta: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Prasenjit Basu, Sayantan Das, Pallab Dasgupta, Partha Pratim Chakrabarti
    Discovering the input assumptions in specification refinement coverage. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:13-18 [Conf]
  2. Pallab Dasgupta, Arindam Chakrabarti, P. P. Chakrabarti
    Open Computation Tree Logic for Formal Verification of Modules. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2002, pp:735-740 [Conf]
  3. Ansuman Banerjee, Bhaskar Pal, Sayantan Das, Abhijeet Kumar, Pallab Dasgupta
    Test generation games from formal specifications. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:827-832 [Conf]
  4. Arindam Chakrabarti, Pallab Dasgupta, P. P. Chakrabarti, Ansuman Banerjee
    Formal verification of module interfaces against real time specifications. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:141-145 [Conf]
  5. Prasenjit Basu, Sayantan Das, Pallab Dasgupta, P. P. Chakrabarti, Chunduri Rama Mohan, Limor Fix
    Formal Verification Coverage: Are the RTL-Properties Covering the Design's Architectural Intent? [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:668-669 [Conf]
  6. Sayantan Das, Prasenjit Basu, Pallab Dasgupta, P. P. Chakrabarti
    What lies between design intent coverage and model checking? [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:1217-1222 [Conf]
  7. Sayantan Das, Rizi Mohanty, Pallab Dasgupta, P. P. Chakrabarti
    Synthesis of system verilog assertions. [Citation Graph (0, 0)][DBLP]
    DATE Designers' Forum, 2006, pp:70-75 [Conf]
  8. Pallab Dasgupta, P. P. Chakrabarti, Amit Nandi, Sekar Krishna, Arindam Chakrabarti
    Abstraction of word-level linear arithmetic functions from bit-level component descriptions. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:4-8 [Conf]
  9. Pallab Dasgupta, P. P. Chakrabarti, S. C. De Sarkar
    A Near Optimal Algorithm for the Extended Cow-Path Problem in the Presence of Relative Errors. [Citation Graph (0, 0)][DBLP]
    FSTTCS, 1995, pp:22-36 [Conf]
  10. Pallab Dasgupta, P. P. Chakrabarti, S. C. De Sarkar
    A New Competitive Algorithm for Agent Searching in Unknown Streets. [Citation Graph (0, 0)][DBLP]
    FSTTCS, 1996, pp:147-155 [Conf]
  11. Prashanti Das, Dibyendu Das, Pallab Dasgupta
    Adaptive Algorithms for Scheduling Static Task Graphs in Dynamic Distributed Systems. [Citation Graph (0, 0)][DBLP]
    HiPC, 1999, pp:143-150 [Conf]
  12. Sayantan Das, Prasenjit Basu, Ansuman Banerjee, Pallab Dasgupta, P. P. Chakrabarti, Chunduri Rama Mohan, Limor Fix, Roy Armoni
    Formal verification coverage: computing the coverage gap between temporal specifications. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2004, pp:198-203 [Conf]
  13. Suchismita Roy, Sayantan Das, Prasenjit Basu, Pallab Dasgupta, Partha Pratim Chakrabarti
    SAT based solutions for consistency problems in formal property specifications for open systems. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2005, pp:885-888 [Conf]
  14. Ansuman Banerjee, Pallab Dasgupta, Partha Pratim Chakrabarti
    Open computation tree logic with fairness. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:249-252 [Conf]
  15. S. Sriram, R. Tandon, Pallab Dasgupta, P. P. Chakrabarti
    Symbolic verification of Boolean constraints over partially specified functions. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:113-116 [Conf]
  16. Jatindra Kumar Deka, S. Chaki, Pallab Dasgupta, P. P. Chakrabarti
    Abstractions for model checking of event timings. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:125-128 [Conf]
  17. Krishnendu Chatterjee, Pallab Dasgupta, P. P. Chakrabarti
    Complexity of Compositional Model Checking of Computation Tree Logic on Simple Structures. [Citation Graph (0, 0)][DBLP]
    IWDC, 2004, pp:102-113 [Conf]
  18. Bhaskar Pal, Ansuman Banerjee, Pallab Dasgupta, P. P. Chakrabarti
    The BUSpec platform for automated generation of verification aids for standard bus protocols. [Citation Graph (0, 0)][DBLP]
    MEMOCODE, 2004, pp:119-128 [Conf]
  19. Diganchal Chakraborty, P. P. Chakrabarti, Arijit Mondal, Pallab Dasgupta
    A Framework for Estimating Peak Power in Gate-Level Circuits. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2006, pp:573-582 [Conf]
  20. Ansuman Banerjee, Pallab Dasgupta, P. P. Chakrabarti
    Formal Verification of Modules under Real Time Environment Constraints. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2004, pp:103-108 [Conf]
  21. Prasenjit Basu, Pallab Dasgupta, P. P. Chakrabarti
    Syntactic Transformation of Assume-Guarantee Assertions: From Sub-Modules to Modules. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2005, pp:213-218 [Conf]
  22. Prasenjit Basu, Pallab Dasgupta, P. P. Chakrabarti, Chunduri Rama Mohan
    Property Refinement Techniques for Enhancing Coverage of Formal Property Verification. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2004, pp:109-114 [Conf]
  23. Pankaj Chauhan, Pallab Dasgupta, P. P. Chakrabarti
    Exploiting Isomorphism for Compaction and Faster Simulation of Binary Decision Diagrams. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1999, pp:324-0 [Conf]
  24. Partha Pratim Chakrabarti, Pallab Dasgupta, Partha Pratim Das, Arnob Roy, Shuvendu K. Lahiri, Mrinal Bose
    Controlling State Explosion in Static Simulation by Selective Composition. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1999, pp:226-231 [Conf]
  25. Jatindra Kumar Deka, Pallab Dasgupta, P. P. Chakrabarti
    An Efficiently Checkable Subset of TCTL for Formal Verification of Transition Systems with Delays. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1999, pp:294-299 [Conf]
  26. Pallab Dasgupta, Prasenjit Mitra, P. P. Chakrabarti, S. C. De Sarkar
    Multiobjective Search in VLSI Design. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1994, pp:395-400 [Conf]
  27. Sayantan Das, Ansuman Banerjee, Prasenjit Basu, Pallab Dasgupta, P. P. Chakrabarti, Chunduri Rama Mohan, Limor Fix
    Formal Methods for Analyzing the Completeness of an Assertion Suite against a High-Level Fault Model. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2005, pp:201-206 [Conf]
  28. Samik Das, P. P. Chakrabarti, Pallab Dasgupta
    Instruction-Set-Extension Exploration Using Decomposable Heuristic Search. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:293-298 [Conf]
  29. Pallab Dasgupta, Arindam Chakrabarti, P. P. Chakrabarti
    Open Computation Tree Logic for Formal Verification of Modules. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:735-740 [Conf]
  30. Sayak Ray, Pallab Dasgupta, P. P. Chakrabarti
    A New Pseudo-Boolean Satisfiability based approach to Power Mode Schedulability Analysis. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2007, pp:95-102 [Conf]
  31. Suchismita Roy, P. P. Chakrabarti, Pallab Dasgupta
    Bounded Delay Timing Analysis Using Boolean Satisfiability. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2007, pp:295-302 [Conf]
  32. Arijit Mondal, P. P. Chakrabarti, Pallab Dasgupta
    Timing Analysis of Sequential Circuits Using Symbolic Event Propagation. [Citation Graph (0, 0)][DBLP]
    ICCTA, 2007, pp:151-157 [Conf]
  33. Pallab Dasgupta, P. P. Chakrabarti, S. C. De Sarkar
    Agent Searching in a Tree and the Optimality of Iterative Deepening. [Citation Graph (0, 0)][DBLP]
    Artif. Intell., 1994, v:71, n:1, pp:195-208 [Journal]
  34. Pallab Dasgupta, P. P. Chakrabarti, S. C. De Sarkar
    A Correction to "Agent Searching in a Tree and the Optimality of Iterative Deepening". [Citation Graph (0, 0)][DBLP]
    Artif. Intell., 1995, v:77, n:1, pp:173-176 [Journal]
  35. Pallab Dasgupta, P. P. Chakrabarti, S. C. De Sarkar
    Searching Game Trees under a Partial Order. [Citation Graph (0, 0)][DBLP]
    Artif. Intell., 1996, v:82, n:1-2, pp:237-257 [Journal]
  36. Pallab Dasgupta, P. P. Chakrabarti, Jatindra Kumar Deka, Sriram Sankaranarayanan
    Min-max Computation Tree Logic. [Citation Graph (0, 0)][DBLP]
    Artif. Intell., 2001, v:127, n:1, pp:137-162 [Journal]
  37. Krishnendu Chatterjee, Pallab Dasgupta, P. P. Chakrabarti
    The power of first-order quantification over states in branching and linear time temporal logics. [Citation Graph (0, 0)][DBLP]
    Inf. Process. Lett., 2004, v:91, n:5, pp:201-210 [Journal]
  38. Pallab Dasgupta
    Agreement under Faulty Interfaces. [Citation Graph (0, 0)][DBLP]
    Inf. Process. Lett., 1998, v:65, n:3, pp:125-129 [Journal]
  39. Pallab Dasgupta, P. P. Chakrabarti, S. C. De Sarkar
    Utility of Pathmax in Partial Order Heuristic Search. [Citation Graph (0, 0)][DBLP]
    Inf. Process. Lett., 1995, v:55, n:6, pp:317-322 [Journal]
  40. Pallab Dasgupta, P. P. Chakrabarti, S. C. De Sarkar
    Agent Search in Uniform b-Ary Trees: Multiple Goals and Unequal Costs. [Citation Graph (0, 0)][DBLP]
    Inf. Process. Lett., 1996, v:58, n:6, pp:311-318 [Journal]
  41. Anindya C. Patthak, Indrajit Bhattacharya, Anirban Dasgupta, Pallab Dasgupta, P. P. Chakrabarti
    Quantified Computation Tree Logic. [Citation Graph (0, 0)][DBLP]
    Inf. Process. Lett., 2002, v:82, n:3, pp:123-129 [Journal]
  42. Pallab Dasgupta, P. P. Chakrabarti, S. C. De Sarkar
    Multiobjektive Heuristic Search in AND/OR Graphs. [Citation Graph (0, 0)][DBLP]
    J. Algorithms, 1996, v:20, n:2, pp:282-311 [Journal]
  43. Krishnendu Chatterjee, Pallab Dasgupta, P. P. Chakrabarti
    A Branching Time Temporal Framework for Quantitative Reasoning. [Citation Graph (0, 0)][DBLP]
    J. Autom. Reasoning, 2003, v:30, n:2, pp:205-232 [Journal]
  44. Dibyendu Das, Pallab Dasgupta, Prashanti Das
    A Heuristic for the Maximum Processor Requirement for Scheduling Layered Task Graphs with Coloring. [Citation Graph (0, 0)][DBLP]
    J. Parallel Distrib. Comput., 1998, v:49, n:2, pp:169-181 [Journal]
  45. Pallab Dasgupta, A. K. Majumder, P. Bhattacharya
    V_THR: An Adaptive Load Balancing Algorithm. [Citation Graph (0, 0)][DBLP]
    J. Parallel Distrib. Comput., 1997, v:42, n:2, pp:101-108 [Journal]
  46. Prasenjit Basu, Sayantan Das, Ansuman Banerjee, Pallab Dasgupta, P. P. Chakrabarti, Chunduri Rama Mohan, Limor Fix, Roy Armoni
    Design-Intent Coverage - A New Paradigm for Formal Property Verification. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:10, pp:1922-1934 [Journal]
  47. Pallab Dasgupta, Jatindra Kumar Deka, Partha Pratim Chakrabarti
    Model checking on timed-event structures. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:5, pp:601-611 [Journal]
  48. Pallab Dasgupta, P. P. Chakrabarti, Arnab Dey, Sujoy Ghose, Wolfgang Bibel
    Solving Constraint Optimization Problems from CLP-Style Specifications Using Heuristic Search Techniques. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Knowl. Data Eng., 2002, v:14, n:2, pp:353-368 [Journal]
  49. Ansuman Banerjee, Pallab Dasgupta
    The open family of temporal logics: Annotating temporal operators with input constraints. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2005, v:10, n:3, pp:492-522 [Journal]
  50. Ansuman Banerjee, Pallab Dasgupta, P. P. Chakrabarti
    Formal methods for checking realizability of coalitions in 3-party systems. [Citation Graph (0, 0)][DBLP]
    MEMOCODE, 2006, pp:198- [Conf]
  51. Bhaskar Pal, Ansuman Banerjee, Pallab Dasgupta, P. P. Chakrabarti
    BUSpec: A framework for generation of verification aids for standard bus protocol specifications. [Citation Graph (0, 0)][DBLP]
    Integration, 2007, v:40, n:3, pp:285-304 [Journal]
  52. Suchismita Roy, P. P. Chakrabarti, Pallab Dasgupta
    Event propagation for accurate circuit delay calculation using SAT. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2007, v:12, n:3, pp:- [Journal]

  53. A Query based Formal Security Analysis Framework for Enterprise LAN. [Citation Graph (, )][DBLP]


  54. CheckSpec: A Tool for Consistency and Coverage Analysis of Assertion Specifications. [Citation Graph (, )][DBLP]


  55. A Dynamic Assertion-Based Verification Platform for Validation of UML Designs. [Citation Graph (, )][DBLP]


  56. Leveraging UPF-extracted assertions for modeling and formal verification of architectural power intent. [Citation Graph (, )][DBLP]


  57. A formal approach for specification-driven AMS behavioral model generation. [Citation Graph (, )][DBLP]


  58. Taming the component timing: A CBD methodology for real-time embedded systems. [Citation Graph (, )][DBLP]


  59. Formal Verification of Security Policy Implementations in Enterprise Networks. [Citation Graph (, )][DBLP]


  60. Cohesive Coverage Management for Simulation and Formal Property Verification. [Citation Graph (, )][DBLP]


  61. Inline Assertions - Embedding Formal Properties in a Test Bench. [Citation Graph (, )][DBLP]


  62. Accelerating Synchronous Sequential Circuits Using an Adaptive Clock. [Citation Graph (, )][DBLP]


  63. Coverage Management with Inline Assertions and Formal Test Points. [Citation Graph (, )][DBLP]


  64. Fault Analysis of Security Policy Implementations in Enterprise Networks. [Citation Graph (, )][DBLP]


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