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Henk Corporaal: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Ireneusz Karkowski, Henk Corporaal
    Design of Heterogenous Multi-Processor Embedded Systems: Applying Functional Pipelining. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 1997, pp:156-165 [Conf]
  2. Ireneusz Karkowski, Henk Corporaal
    Exploiting Fine- and Coarse-Grain Parallelism in Embedded Programs. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 1998, pp:60-67 [Conf]
  3. Hamed Fatemi, Henk Corporaal, Twan Basten, Richard P. Kleihorst, Pieter P. Jonker
    Designing Area and Performance Constrained SIMD/VLIW Image Processing Architectures. [Citation Graph (0, 0)][DBLP]
    ACIVS, 2005, pp:689-696 [Conf]
  4. Wilco Van Hoogstraeten, Henk Corporaal
    ADVISE: Performance Evaluation of Parallel VHDL Simulation. [Citation Graph (0, 0)][DBLP]
    Annual Simulation Symposium, 1997, pp:146-156 [Conf]
  5. Andy Lambrechts, Praveen Raghavan, Anthony Leroy, Guillermo Talavera, Tom Vander Aa, Murali Jayapala, Francky Catthoor, Diederik Verkest, Geert Deconinck, Henk Corporaal, Frédéric Robert, Jordi Carrabina
    Power Breakdown Analysis for a Heterogeneous NoC Platform Running a Video Application. [Citation Graph (0, 0)][DBLP]
    ASAP, 2005, pp:179-184 [Conf]
  6. Bart Mesman, Hamed Fatemi, Henk Corporaal, Twan Basten
    Dynamic-SIMD for lens distortion compensation. [Citation Graph (0, 0)][DBLP]
    ASAP, 2006, pp:261-264 [Conf]
  7. Tom Vander Aa, Murali Jayapala, Francisco Barat, Geert Deconinck, Rudy Lauwereins, Francky Catthoor, Henk Corporaal
    Instruction buffering exploration for low energy VLIWs with instruction clusters. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:824-829 [Conf]
  8. Jinfeng Huang, Marc Geilen, Jeroen Voeten, Henk Corporaal
    Branching-Time Property Preservation Between Real-Time Systems. [Citation Graph (0, 0)][DBLP]
    ATVA, 2006, pp:260-275 [Conf]
  9. Stefan Valentin Gheorghita, Twan Basten, Henk Corporaal
    Intra-task scenario-aware voltage scheduling. [Citation Graph (0, 0)][DBLP]
    CASES, 2005, pp:177-184 [Conf]
  10. Andrei Terechko, Erwan Le Thenaff, Henk Corporaal
    Cluster assignment of global values for clustered VLIW processors. [Citation Graph (0, 0)][DBLP]
    CASES, 2003, pp:32-40 [Conf]
  11. Johan Janssen, Henk Corporaal
    Controlled Node Splitting. [Citation Graph (0, 0)][DBLP]
    CC, 1996, pp:44-58 [Conf]
  12. Andrea G. M. Cilio, Henk Corporaal
    Global Variable Promotion: Using Registers to Reduce Cache Power Dissipation. [Citation Graph (0, 0)][DBLP]
    CC, 2002, pp:247-260 [Conf]
  13. Maarten Boekhold, Ireneusz Karkowski, Henk Corporaal, Andrea G. M. Cilio
    A Programmable ANSI C Transformation Engine. [Citation Graph (0, 0)][DBLP]
    CC, 1999, pp:292-295 [Conf]
  14. Andrea G. M. Cilio, Henk Corporaal
    Floating Point to Fixed Point Conversion of C Code. [Citation Graph (0, 0)][DBLP]
    CC, 1999, pp:229-243 [Conf]
  15. Jan Hoogerbrugge, Henk Corporaal
    Comparing Software Pipelining for an Operation-Triggered and a Tarnsport-Triggered Architecture. [Citation Graph (0, 0)][DBLP]
    CC, 1992, pp:219-228 [Conf]
  16. Jan Hoogerbrugge, Henk Corporaal
    Transport-Triggering versus Operation-Triggering. [Citation Graph (0, 0)][DBLP]
    CC, 1994, pp:435-449 [Conf]
  17. Marnix Arnold, Henk Corporaal
    Designing domain-specific processors. [Citation Graph (0, 0)][DBLP]
    CODES, 2001, pp:61-66 [Conf]
  18. Marnix Arnold, Henk Corporaal
    Automatic detection of recurring operation patterns. [Citation Graph (0, 0)][DBLP]
    CODES, 1999, pp:22-26 [Conf]
  19. Stefan Valentin Gheorghita, Sander Stuijk, Twan Basten, Henk Corporaal
    Automatic scenario detection for improved WCET estimation. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:101-104 [Conf]
  20. Ireneusz Karkowski, Henk Corporaal
    Design Space Exploration Algorithm for Heterogeneous Multi-Processor Embedded System Design. [Citation Graph (0, 0)][DBLP]
    DAC, 1998, pp:82-87 [Conf]
  21. Henk Corporaal, Jan Hoogerbrugge
    Code generation for transport triggered architectures. [Citation Graph (0, 0)][DBLP]
    Code Generation for Embedded Processors, 1994, pp:240-259 [Conf]
  22. Erik Brockmeyer, Miguel Miranda, Henk Corporaal, Francky Catthoor
    Layer Assignment echniques for Low Energy in Multi-Layered Memory Organisations. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:11070-11075 [Conf]
  23. Paul Marchal, José Ignacio Gómez, Luis Piñuel, Davide Bruni, Luca Benini, Francky Catthoor, Henk Corporaal
    SDRAM-Energy-Aware Memory Allocation for Dynamic Multi-Media Applications on Multi-Processor Platforms. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10516-10523 [Conf]
  24. Akash Kumar, Bart Mesman, Henk Corporaal, Jef L. van Meerbergen, Yajun Ha
    Global Analysis of Resource Arbitration for MPSoC. [Citation Graph (0, 0)][DBLP]
    DSD, 2006, pp:71-78 [Conf]
  25. Henk Corporaal
    Distributed Heapmanagement using reference weights. [Citation Graph (0, 0)][DBLP]
    EDMCC, 1991, pp:325-336 [Conf]
  26. Henk Corporaal, J. G. E. Olk
    A Scalable Communication Processor Design supporting Systolic Communication. [Citation Graph (0, 0)][DBLP]
    EDMCC, 1991, pp:213-223 [Conf]
  27. Prabhat Avasare, Vincent Nollet, Jean-Yves Mignolet, Diederik Verkest, Henk Corporaal
    Centralized end-to-end flow control in a best-effort network-on-chip. [Citation Graph (0, 0)][DBLP]
    EMSOFT, 2005, pp:17-20 [Conf]
  28. Vincent Nollet, Prabhat Avasare, Diederik Verkest, Henk Corporaal
    Exploiting Hierarchical Configuration to Improve Run-Time MPSoC Task Assignment. [Citation Graph (0, 0)][DBLP]
    ERSA, 2006, pp:49-55 [Conf]
  29. Tom Vander Aa, Francky Catthoor, Henk Corporaal, Geert Deconinck
    Combining Data and Instruction Memory Energy Optimizations for Embedded Applications. [Citation Graph (0, 0)][DBLP]
    ESTImedia, 2005, pp:121-126 [Conf]
  30. Théodore Marescaux, B. Bricke, P. Debacker, Vincent Nollet, Henk Corporaal
    Dynamic Time-Slot Allocation for QoS Enabled Networks on Chip. [Citation Graph (0, 0)][DBLP]
    ESTImedia, 2005, pp:47-52 [Conf]
  31. Rashindra Manniesing, Ireneusz Karkowski, Henk Corporaal
    Automatic SIMD Parallelization of Embedded Applications Based on Pattern Recognition. [Citation Graph (0, 0)][DBLP]
    Euro-Par, 2000, pp:349-356 [Conf]
  32. Henjo Schot, Henk Corporaal
    Automated Design of an ASIP for Image Processing Applications (Research Note). [Citation Graph (0, 0)][DBLP]
    Euro-Par, 2000, pp:1105-1109 [Conf]
  33. Marian Stanca, Stamatis Vassiliadis, Sorin Cotofana, Henk Corporaal
    Hashed Addressed Caches for Embedded Pointer Based Codes (Research Note). [Citation Graph (0, 0)][DBLP]
    Euro-Par, 2000, pp:965-968 [Conf]
  34. Eddy Ok, Henk Corporaal
    Application Driven MIMD Communication Processor Design. [Citation Graph (0, 0)][DBLP]
    EUROSIM, 1994, pp:609-616 [Conf]
  35. Francisco Barat, Murali Jayapala, Tom Vander Aa, Rudy Lauwereins, Geert Deconinck, Henk Corporaal
    Low Power Coarse-Grained Reconfigurable Instruction Set Processor. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:230-239 [Conf]
  36. Andrei Terechko, Erwan Le Thenaff, Manish Garg, Jos T. J. van Eijndhoven, Henk Corporaal
    Inter-Cluster Communication Models for Clustered VLIW Processors. [Citation Graph (0, 0)][DBLP]
    HPCA, 2003, pp:354-364 [Conf]
  37. Maarten Boekhold, Ireneusz Karkowski, Henk Corporaal
    Transformatiing and Parallelizing ANSI C Programs using Pattern Recognition. [Citation Graph (0, 0)][DBLP]
    HPCN Europe, 1999, pp:673-682 [Conf]
  38. Andrea G. M. Cilio, Henk Corporaal
    Code Positioning for VLIW Architectures. [Citation Graph (0, 0)][DBLP]
    HPCN Europe, 2001, pp:332-343 [Conf]
  39. Andrea G. M. Cilio, Henk Corporaal
    A Linker for effective Whole-Program Optimization. [Citation Graph (0, 0)][DBLP]
    HPCN Europe, 1999, pp:643-652 [Conf]
  40. Jeroen Hordijk, Henk Corporaal
    The Potential of Exploiting Coarse-Grain Task Parallelism from Sequential Programs. [Citation Graph (0, 0)][DBLP]
    HPCN Europe, 1997, pp:664-673 [Conf]
  41. Ireneusz Karkowski, Henk Corporaal
    Overcoming the Limitations of the Traditional Loop Parallelization. [Citation Graph (0, 0)][DBLP]
    HPCN Europe, 1997, pp:898-907 [Conf]
  42. Hamed Fatemi, Bart Mesman, Henk Corporaal, Twan Basten, Pieter P. Jonker
    Run-time reconfiguration of communication in SIMD architectures. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2006, pp:- [Conf]
  43. Wouter Caarls, Pieter P. Jonker, Henk Corporaal
    Algorithmic skeletons for stream programming in embedded heterogeneous parallel image processing applications. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2006, pp:- [Conf]
  44. Jari Heikkinen, Andrea G. M. Cilio, Jarmo Takala, Henk Corporaal
    Dictionary-based program compression on transport triggered architectures. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1122-1125 [Conf]
  45. Panu Hämäläinen, Marko Hännikäinen, Timo Hämäläinen, Henk Corporaal, Jukka Saarinen
    Implementation of encryption algorithms on transport triggered architectures. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:726-729 [Conf]
  46. Jari Heikkinen, Tommi Rantanen, Andrea G. M. Cilio, Jarmo Takala, Henk Corporaal
    Evaluating Template-Based Instruction Compression on Transport Triggered Architectures. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2003, pp:192-195 [Conf]
  47. Peter Vanbroekhoven, Henk Corporaal, Francky Catthoor
    Advanced copy propagation for arrays. [Citation Graph (0, 0)][DBLP]
    LCTES, 2003, pp:24-33 [Conf]
  48. Johan Janssen, Henk Corporaal
    Partitioned register file for TTAs. [Citation Graph (0, 0)][DBLP]
    MICRO, 1995, pp:303-312 [Conf]
  49. A. J. van de Goor, Henk Corporaal
    DOAS: an object oriented architecture supporting secure languages. [Citation Graph (0, 0)][DBLP]
    MICRO, 1989, pp:127-134 [Conf]
  50. Jan Hoogerbrugge, Henk Corporaal
    Register file port requirements of transport triggered architectures. [Citation Graph (0, 0)][DBLP]
    MICRO, 1994, pp:191-195 [Conf]
  51. Jan Hoogerbrugge, Henk Corporaal, Hans Mulder
    Software Pipelining for Transport-Triggered Architectures. [Citation Graph (0, 0)][DBLP]
    MICRO, 1991, pp:74-81 [Conf]
  52. Théodore Marescaux, A. Rangevall, Vincent Nollet, Andrei Bartic, Henk Corporaal
    Distributed Congestion Control for Packet Switched Networks on Chip. [Citation Graph (0, 0)][DBLP]
    PARCO, 2005, pp:761-768 [Conf]
  53. J. G. E. Olk, Henk Corporaal
    The OSI Model Applied to MIMD Communication Processor Design. [Citation Graph (0, 0)][DBLP]
    PARCO, 1993, pp:403-410 [Conf]
  54. Tom Vander Aa, Murali Jayapala, Francisco Barat, Geert Deconinck, Rudy Lauwereins, Henk Corporaal, Francky Catthoor
    Instruction Buffering Exploration for Low Energy Embedded Processors. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2003, pp:409-419 [Conf]
  55. Murali Jayapala, Tom Vander Aa, Francisco Barat, Francky Catthoor, Henk Corporaal, Geert Deconinck
    L0 Cluster Synthesis and Operation Shuffling. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2004, pp:311-321 [Conf]
  56. Murali Jayapala, Francisco Barat, Pieter Op de Beeck, Francky Catthoor, Geert Deconinck, Henk Corporaal
    A Low Energy Clustered Instruction Memory Hierarchy for Long Instruction Word Processors. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2002, pp:258-267 [Conf]
  57. Martin Palkovic, Erik Brockmeyer, Peter Vanbroekhoven, Henk Corporaal, Francky Catthoor
    Systematic Preprocessing of Data Dependent Constructs for Embedded Systems. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2005, pp:89-98 [Conf]
  58. Jinfeng Huang, Jeroen Voeten, Henk Corporaal
    Correctness-preserving synthesis for real-time control software. [Citation Graph (0, 0)][DBLP]
    QSIC, 2006, pp:65-73 [Conf]
  59. Oana Florescu, Jinfeng Huang, Jeroen Voeten, Henk Corporaal
    Strengthening Property Preservation in Concurrent Real-Time Systems. [Citation Graph (0, 0)][DBLP]
    RTCSA, 2006, pp:106-109 [Conf]
  60. Andy Lambrechts, Tom Vander Aa, Murali Jayapala, Guillermo Talavera, Anthony Leroy, Adelina Shickova, Francisco Barat, Bingfeng Mei, Francky Catthoor, Diederik Verkest, Geert Deconinck, Henk Corporaal, Frédéric Robert, Jordi Carrabina Bordoll
    Design Style Case Study for Embedded Multi Media Compute Nodes. [Citation Graph (0, 0)][DBLP]
    RTSS, 2004, pp:104-113 [Conf]
  61. Murali Jayapala, Tom Vander Aa, Francisco Barat, Geert Deconinck, Francky Catthoor, Henk Corporaal
    L0 buffer energy optimization through scheduling and exploration. [Citation Graph (0, 0)][DBLP]
    SAC, 2004, pp:905-906 [Conf]
  62. Oana Florescu, Menno de Hoon, Jeroen Voeten, Henk Corporaal
    Probabilistic Modelling and Evaluation of Soft Real-Time Embedded Systems. [Citation Graph (0, 0)][DBLP]
    SAMOS, 2006, pp:206-215 [Conf]
  63. Henk Corporaal, Hans Mulder
    MOVE: a framework for high-performance processor design. [Citation Graph (0, 0)][DBLP]
    SC, 1991, pp:692-701 [Conf]
  64. Martin Palkovic, Henk Corporaal, Francky Catthoor
    Global Memory Optimisation for Embedded Systems Allowed by Code Duplication. [Citation Graph (0, 0)][DBLP]
    SCOPES, 2005, pp:72-79 [Conf]
  65. Qin Zhao, Bart Mesman, Henk Corporaal
    Limited Address Range Architecture for Reducing Code Size in Embedded Processors. [Citation Graph (0, 0)][DBLP]
    SCOPES, 2003, pp:2-16 [Conf]
  66. Antonis Papanikolaou, Miguel Miranda, Francky Catthoor, Henk Corporaal, Hugo De Man, David De Roest, Michele Stucchi, Karen Maex
    Global interconnect trade-off for technology over memory modules to application level: case study. [Citation Graph (0, 0)][DBLP]
    SLIP, 2003, pp:125-132 [Conf]
  67. Antonis Papanikolaou, Miguel Miranda, Francky Catthoor, Henk Corporaal, Hugo De Man, David De Roest, Michele Stucchi, Karen Maex
    Interconnect exploration for future wire dominated technologies. [Citation Graph (0, 0)][DBLP]
    SLIP, 2002, pp:105-106 [Conf]
  68. Andrei Terechko, Manish Garg, Henk Corporaal
    Evaluation of Speed and Area of Clustered VLIW Processors. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2005, pp:557-563 [Conf]
  69. Henk Corporaal, Johan Janssen, Marnix Arnold
    Computation in the Context of Transport Triggered Architectures. [Citation Graph (0, 0)][DBLP]
    International Journal of Parallel Programming, 2000, v:28, n:4, pp:401-427 [Journal]
  70. Murali Jayapala, Francisco Barat, Tom Vander Aa, Francky Catthoor, Henk Corporaal, Geert Deconinck
    Clustered Loop Buffer Organization for Low Energy VLIW Embedded Processors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2005, v:54, n:6, pp:672-683 [Journal]
  71. Johan Janssen, Henk Corporaal
    Making Graphs Reducible with Controlled Node Splitting. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Program. Lang. Syst., 1997, v:19, n:6, pp:1031-1052 [Journal]
  72. Jinfeng Huang, Jeroen Voeten, Marcel Groothuis, Jan F. Broenink, Henk Corporaal
    A model-driven design approach for mechatronic systems. [Citation Graph (0, 0)][DBLP]
    ACSD, 2007, pp:127-136 [Conf]
  73. Akash Kumar, Bart Mesman, Henk Corporaal, Bart D. Theelen, Yajun Ha
    A Probabilistic Approach to Model Resource Contention for Performance Estimation of Multi-featured Media Devices. [Citation Graph (0, 0)][DBLP]
    DAC, 2007, pp:726-731 [Conf]
  74. Théodore Marescaux, Henk Corporaal
    Introducing the SuperGT Network-on-Chip; SuperGT QoS: more than just GT. [Citation Graph (0, 0)][DBLP]
    DAC, 2007, pp:116-121 [Conf]
  75. Sander Stuijk, Twan Basten, Marc Geilen, Henk Corporaal
    Multiprocessor Resource Allocation for Throughput-Constrained Synchronous Dataflow Graphs. [Citation Graph (0, 0)][DBLP]
    DAC, 2007, pp:777-782 [Conf]
  76. Praveen Raghavan, Andy Lambrechts, Murali Jayapala, Francky Catthoor, Diederik Verkest, Henk Corporaal
    Very wide register: an asymmetric register file organization for low power embedded processors. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:1066-1071 [Conf]
  77. Akash Kumar, Andreas Hansson, Jos Huisken, Henk Corporaal
    Interactive presentation: An FPGA design flow for reconfigurable network-based multi-processor systems on chip. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:117-122 [Conf]
  78. Stefan Valentin Gheorghita, Twan Basten, Henk Corporaal
    Profiling Driven Scenarion Detection and Prediction for Multimedia Applications. [Citation Graph (0, 0)][DBLP]
    ICSAMOS, 2006, pp:63-70 [Conf]
  79. Chantal Ykman-Couvreur, Vincent Nollet, Théodore Marescaux, Erik Brockmeyer, Francky Catthoor, Henk Corporaal
    Pareto-Based Application Specification for MP-SoC Customized Run-Time Management. [Citation Graph (0, 0)][DBLP]
    ICSAMOS, 2006, pp:78-84 [Conf]
  80. Théodore Marescaux, Erik Brockmeyer, Henk Corporaal
    The Impact of Higher Communication Layers on NoC Supported MP-SoCs. [Citation Graph (0, 0)][DBLP]
    NOCS, 2007, pp:107-116 [Conf]
  81. Andrea G. M. Cilio, Henk Corporaal
    Link-time effective whole-program optimizations. [Citation Graph (0, 0)][DBLP]
    Future Generation Comp. Syst., 2000, v:16, n:5, pp:503-511 [Journal]
  82. Jinfeng Huang, Jeroen Voeten, Henk Corporaal
    Predictable real-time software synthesis. [Citation Graph (0, 0)][DBLP]
    Real-Time Systems, 2007, v:36, n:3, pp:159-198 [Journal]
  83. Andrei Terechko, Henk Corporaal
    Inter-cluster communication in VLIW architectures. [Citation Graph (0, 0)][DBLP]
    TACO, 2007, v:4, n:2, pp:- [Journal]
  84. Martin Palkovic, Erik Brockmeyer, Peter Vanbroekhoven, Henk Corporaal, Francky Catthoor
    Systematic Preprocessing of Data Dependent Constructs for Embedded Systems. [Citation Graph (0, 0)][DBLP]
    J. Low Power Electronics, 2006, v:2, n:1, pp:9-1 [Journal]

  85. Real-Time Hough Transform on 1-D SIMD Processors: Implementation and Architecture Exploration. [Citation Graph (, )][DBLP]


  86. Distributed Smart Camera Calibration Using Blinking LED. [Citation Graph (, )][DBLP]


  87. Statistical noise margin estimation for sub-threshold combinational circuits. [Citation Graph (, )][DBLP]


  88. A predictable communication assist. [Citation Graph (, )][DBLP]


  89. Analytics for the internet of things. [Citation Graph (, )][DBLP]


  90. Intra- and inter-processor hybrid performance modeling for MPSoC architectures. [Citation Graph (, )][DBLP]


  91. A tuneable software cache coherence protocol for heterogeneous MPSoCs. [Citation Graph (, )][DBLP]


  92. Xetal-Pro: an ultra-low energy and high throughput SIMD processor. [Citation Graph (, )][DBLP]


  93. Fast and accurate protocol specific bus modeling using TLM 2.0. [Citation Graph (, )][DBLP]


  94. Automated bottleneck-driven design-space exploration of media processing systems. [Citation Graph (, )][DBLP]


  95. Exploring trade-offs between performance and resource requirements for synchronous dataflow graphs. [Citation Graph (, )][DBLP]


  96. Resource Manager for Non-preemptive Heterogeneous Multiprocessor System-on-chip. [Citation Graph (, )][DBLP]


  97. A new flexible VHDL simulator. [Citation Graph (, )][DBLP]


  98. QoS Management for Wireless Sensor Networks with a Mobile Sink. [Citation Graph (, )][DBLP]


  99. Multi-processor System-level Synthesis for Multiple Applications on Platform FPGA. [Citation Graph (, )][DBLP]


  100. DC-SIMD : Dynamic communication for SIMD processors. [Citation Graph (, )][DBLP]


  101. Vt balancing and device sizing towards high yield of sub-threshold static logic gates. [Citation Graph (, )][DBLP]


  102. A Unified Model for Analysis of Real-Time Properties. [Citation Graph (, )][DBLP]


  103. Improving Product Usage Monitoring and Analysis with Semantic Concepts. [Citation Graph (, )][DBLP]


  104. Analysing qos trade-offs in wireless sensor networks. [Citation Graph (, )][DBLP]


  105. Performance evaluation of concurrently executing parallel applications on multi-processor systems. [Citation Graph (, )][DBLP]


  106. Model Interpretation for Executable Observation Specifications. [Citation Graph (, )][DBLP]


  107. Specification for User Modeling with Self-Observing Systems. [Citation Graph (, )][DBLP]


  108. Skeletons and Asynchronous RPC for Embedded Data- and Task Parallel Image Processing. [Citation Graph (, )][DBLP]


  109. Enabling MPSoC Design Space Exploration on FPGAs. [Citation Graph (, )][DBLP]


  110. UML Profile for Modeling Product Observation. [Citation Graph (, )][DBLP]


  111. Reusing Real-Time Systems Design Experience. [Citation Graph (, )][DBLP]


  112. Synthesis for Unified Control- and Data-Oriented Models. [Citation Graph (, )][DBLP]


  113. Error Estimation in Model-Driven Development for Real-Time Software. [Citation Graph (, )][DBLP]


  114. Instruction Transfer And Storage Exploration for Low Energy VLIWs. [Citation Graph (, )][DBLP]


  115. Application Scenarios in Streaming-Oriented Embedded-System Design. [Citation Graph (, )][DBLP]


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