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Publications of Author

1. Al Dunlop, Alper Demir, Peter Feldmann, Sharad Kapur, David E. Long, Robert C. Melville, Jaijeet S. Roychowdhury
   Tools and Methodology for RF IC Design. [Citation Graph (0, 0)][DBLP]
   DAC, 1998, pp:414-420 [Conf]
   
2. Peter Feldmann, Roland W. Freund
   Reduced-Order Modeling of Large Linear Subcircuits via a Block Lanczos Algorithm. [Citation Graph (0, 0)][DBLP]
   DAC, 1995, pp:474-479 [Conf]
   
3. Hans Georg Brachtendorf, S. Lampe, Rainer Laur, Robert C. Melville, Peter Feldmann
   Steady State Calculation of Oscillators Using Continuation Methods. [Citation Graph (0, 0)][DBLP]
   DATE, 2002, pp:1139- [Conf]
   
4. Alper Demir, Peter Feldmann
   Stochastic Modeling and Performance Evaluation for Digital Clock and Data Recovery Circuits. [Citation Graph (0, 0)][DBLP]
   DATE, 2000, pp:340-344 [Conf]
   
5. Peter Feldmann, Sharad Kapur, David E. Long
   Efficient Techniques for Modeling Chip-Level Interconnect, Substrate and Package Parasitics. [Citation Graph (0, 0)][DBLP]
   DATE, 1999, pp:418-417 [Conf]
   
6. Peter Feldmann
   Model Order Reduction Techniques for Linear Systems with Large Numbers of Terminals. [Citation Graph (0, 0)][DBLP]
   DATE, 2004, pp:944-947 [Conf]
   
7. Roland W. Freund, Peter Feldmann
   Reduced-Order Modeling of Large Linear Passive Multi-Terminal Circuits Using Matrix-Pade Approximation. [Citation Graph (0, 0)][DBLP]
   DATE, 1998, pp:530-537 [Conf]
   
8. Lun Ye, Foong-Charn Chang, Peter Feldmann, Rakesh Chadha, Nagaraj Ns, Frank Cano
   Chip-Level Verification for Parasitic Coupling Effects in Deep-Submicron Digital Designs. [Citation Graph (0, 0)][DBLP]
   DATE, 1999, pp:658-663 [Conf]
   
9. Alper Demir, Peter Feldmann
   Modelling and Analysis of Communication Circuit Performance Using Markov Chains and Efficient Graph Representations. [Citation Graph (0, 0)][DBLP]
   ICCAD, 2000, pp:290-295 [Conf]
   
10. Alper Demir, Peter Feldmann
    Modeling and simulation of the interference due to digital switching in mixed-signal ICs. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:70-75 [Conf]
    
11. Peter Feldmann, Stephen W. Director
    Accurate and Efficient Evaluation of Circuit Yield and Yield Gradients. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1990, pp:120-123 [Conf]
    
12. Peter Feldmann, Stephen W. Director
    Improved Methods for IC Yield and Quality Optimization Using Surface Integrals. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1991, pp:158-161 [Conf]
    
13. Peter Feldmann, Roland W. Freund
    Circuit noise evaluation by Padé approximation based model-reduction techniques. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1997, pp:132-138 [Conf]
    
14. Peter Feldmann, F. Liu
    Sparse and efficient reduced order modeling of linear subcircuits with large number of terminals. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2004, pp:88-92 [Conf]
    
15. Peter Feldmann, Robert C. Melville, Shahriar Moinian
    Automatic differentiation in circuit simulation and device modeling. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1992, pp:248-253 [Conf]
    
16. Peter Feldmann, Jaijeet S. Roychowdhury
    Computation of circuit waveform envelopes using an efficient, matrix-decomposed harmonic balance algorithm. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1996, pp:295-300 [Conf]
    
17. Roland W. Freund, Peter Feldmann
    Efficient small-signal circuit analysis and sensitivity computations with the PVL algorithm. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1994, pp:404-411 [Conf]
    
18. Roland W. Freund, Peter Feldmann
    Reduced-order modeling of large passive linear circuits by means of the SYPVL algorithm. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1996, pp:280-287 [Conf]
    
19. Chandramouli Visweswariah, Peter Feldmann, Ronald A. Rohrer
    Incorporation of Inductors in Piecewise Approximate Circuit Simulation. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1990, pp:162-165 [Conf]
    
20. Bob Melville, Peter Feldmann, Shahriar Moinian
    AC++ Based Environment for Analog Circuit Simulation. [Citation Graph (0, 0)][DBLP]
    ICCD, 1992, pp:516-519 [Conf]
    
21. Abelardo Pardo, R. Iris Bahar, Srilatha Manne, Peter Feldmann, Gary D. Hachtel, Fabio Somenzi
    CMOS dynamic power estimation based on collapsible current source transistor modeling. [Citation Graph (0, 0)][DBLP]
    ISLPD, 1995, pp:111-116 [Conf]
    
22. Peter Feldmann, Stephen W. Director
    Integrated circuit quality optimization using surface integrals. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:12, pp:1868-1879 [Journal]
    
23. Peter Feldmann, Roland W. Freund
    Efficient linear circuit analysis by Pade approximation via the Lanczos process. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:5, pp:639-649 [Journal]
    
24. Peter Feldmann, Tuyen V. Nguyen, Stephen W. Director, Ronald A. Rohrer
    Sensitivity computation in piecewise approximate circuit simulation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:2, pp:171-183 [Journal]
    
25. Emrah Acar, Peter Feldmann
    Simulation of SOI transistor circuits through non-equilibrium initial condition analysis (NEICA). [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
    
26. 
    Driver waveform computation for timing analysis with multiple voltage threshold driver models. [Citation Graph (, )][DBLP]
    
    
27. 
    Towards a more physical approach to gate modeling for timing, noise, and power. [Citation Graph (, )][DBLP]
    
    
28. 
    A moment-based effective characterization waveform for static timing analysis. [Citation Graph (, )][DBLP]
    
    
29. 
    Efficient compression and handling of current source model library waveforms. [Citation Graph (, )][DBLP]
    
    
30. 
    Efficient linear circuit analysis by Pade´ approximation via the Lanczos process. [Citation Graph (, )][DBLP]
    
    
31. 
    MAISE: An Interconnect Simulation Engine for Timing and Noise Analysis. [Citation Graph (, )][DBLP]