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Publications of Author

1. Subhayu Basu, Debdeep Mukhopadhyay, Dipanwita Roy Chowdhury, Indranil Sengupta, Sudipta Bhawmik
   Reformatting Test Patterns for Testing Embedded Core Based System Using Test Access Mechanism (TAM) Switch. [Citation Graph (0, 0)][DBLP]
   ASP-DAC, 2002, pp:598-603 [Conf]
   
2. Tapan J. Chakraborty, Sudipta Bhawmik, Robert Bencivenga, Chih-Jen Lin
   Enhanced Controllability for I_DDQ Test Sets Using Partial Scan. [Citation Graph (0, 0)][DBLP]
   DAC, 1991, pp:278-281 [Conf]
   
3. Indradeep Ghosh, Niraj K. Jha, Sudipta Bhawmik
   A BIST Scheme for RTL Controller-Data Paths Based on Symbolic Testability Analysis. [Citation Graph (0, 0)][DBLP]
   DAC, 1998, pp:554-559 [Conf]
   
4. Huan-Chih Tsai, Kwang-Ting Cheng, Sudipta Bhawmik
   Improving the Test Quality for Scan-Based BIST Using a General Test Application Scheme. [Citation Graph (0, 0)][DBLP]
   DAC, 1999, pp:748-753 [Conf]
   
5. Huan-Chih Tsai, Kwang-Ting Cheng, Chih-Jen Lin, Sudipta Bhawmik
   A Hybrid Algorithm for Test Point Selection for Scan-Based BIST. [Citation Graph (0, 0)][DBLP]
   DAC, 1997, pp:478-483 [Conf]
   
6. Sudipta Bhawmik, P. Pal Chaudhuri
   DFTEXPERT: An Expert System for Design of Testable VLSI Circuits. [Citation Graph (0, 0)][DBLP]
   IEA/AIE (Vol. 1), 1988, pp:388-396 [Conf]
   
7. Chih-Jen Lin, Yervant Zorian, Sudipta Bhawmik
   PSBIST: A Partial-Scan Based Built-In Self-Test Scheme. [Citation Graph (0, 0)][DBLP]
   ITC, 1993, pp:507-516 [Conf]
   
8. Nilanjan Mukherjee, Tapan J. Chakraborty, Sudipta Bhawmik
   A BIST scheme for the detection of path-delay faults. [Citation Graph (0, 0)][DBLP]
   ITC, 1998, pp:422-0 [Conf]
   
9. Huan-Chih Tsai, Sudipta Bhawmik, Kwang-Ting Cheng
   An almost full-scan BIST solution-higher fault coverage and shorter test application time. [Citation Graph (0, 0)][DBLP]
   ITC, 1998, pp:1065-0 [Conf]
   
10. Michael G. Wahl, Sudipta Bhawmik, Kamran Zarrineh, Pradipta Ghosh, Scott Davidson, Peter Harrod
    The P1500 DFT Disclosure Document: A Standard to Communicate Mergeable Core DFT Data. [Citation Graph (0, 0)][DBLP]
    ITC, 2003, pp:998-1007 [Conf]
    
11. Subhayu Basu, Debdeep Mukhopadhyay, Dipanwita Roy Chowdhury, Indranil Sengupta, Sudipta Bhawmik
    Reformatting Test Patterns for Testing Embedded Core Based System Using Test Access Mechanism (TAM) Switch. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:598-603 [Conf]
    
12. Sudipta Bhawmik
    ntroduction to SystemC. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2001, pp:7-8 [Conf]
    
13. Sudipta Bhawmik, Indradeep Ghosh
    A Practical Method for Selecting Partial Scan Flip-flops for Large Circuits. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:284-288 [Conf]
    
14. Frank P. Higgins, Sudipta Bhawmik
    Core Based ASIC Design. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2000, pp:10- [Conf]
    
15. Xiaodong Zhang, Kaushik Roy, Sudipta Bhawmik
    POWERTEST: A Tool for Energy Conscious Weighted Random Pattern Testing. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1999, pp:416-422 [Conf]
    
16. Prasad R. Chalasani, Sudipta Bhawmik, Anurag Acharya, P. Palchaudhuri
    Design of Testable VLSI Circuits with Minumum Area Overhead. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1989, v:38, n:10, pp:1460-1462 [Journal]
    
17. Indradeep Ghosh, Niraj K. Jha, Sudipta Bhawmik
    A BIST scheme for RTL circuits based on symbolic testabilityanalysis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:1, pp:111-128 [Journal]
    
18. Huan-Chih Tsai, Kwang-Ting Cheng, Sudipta Bhawmik
    On improving test quality of scan-based BIST. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:8, pp:928-938 [Journal]
    
19. Huan-Chih Tsai, Kwang-Ting Cheng, Chih-Jen Lin, Sudipta Bhawmik
    Efficient test-point selection for scan-based BIST. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1998, v:6, n:4, pp:667-676 [Journal]