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Thomas Kropf: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Klaus Schneider, Ramayya Kumar, Thomas Kropf
    The FAUST - Prover. [Citation Graph (0, 0)][DBLP]
    CADE, 1992, pp:766-770 [Conf]
  2. Klaus Schneider, Ramayya Kumar, Thomas Kropf
    Automating Most Parts of Hardware Proofs in HOL. [Citation Graph (0, 0)][DBLP]
    CAV, 1991, pp:365-375 [Conf]
  3. Dirk W. Hoffmann, Thomas Kropf
    Automatic Error Correction of Large Circuits Using Boolean Decomposition and Abstraction. [Citation Graph (0, 0)][DBLP]
    CHARME, 1999, pp:157-171 [Conf]
  4. Thomas Kropf, Ramayya Kumar, Klaus Schneider
    Embedding Hardware Verification Within a Commercial Design Framework. [Citation Graph (0, 0)][DBLP]
    CHARME, 1993, pp:242-257 [Conf]
  5. Jürgen Ruf, Thomas Kropf
    Symbolic model checking for a discrete clocked temporal logic with intervals. [Citation Graph (0, 0)][DBLP]
    CHARME, 1997, pp:146-163 [Conf]
  6. Jürgen Ruf, Thomas Kropf
    Modleing and Checking Networks of Communicating Real-Time Process. [Citation Graph (0, 0)][DBLP]
    CHARME, 1999, pp:265-279 [Conf]
  7. Klaus Schneider, Ramayya Kumar, Thomas Kropf
    Hardware-Verification using First Order BDDs. [Citation Graph (0, 0)][DBLP]
    CHDL, 1993, pp:45-62 [Conf]
  8. Prakash M. Peranandam, Pradeep K. Nalla, Jürgen Ruf, Roland J. Weiss, Thomas Kropf, Wolfgang Rosenstiel
    Fast falsification based on symbolic bounded property checking. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:1077-1082 [Conf]
  9. Dirk W. Hoffmann, Thomas Kropf
    Exploiting Hierarchy for Multiple Error Correction in Combinational Circuits. [Citation Graph (0, 0)][DBLP]
    DATE, 2000, pp:758- [Conf]
  10. Michaela Huhn, Klaus Schneider, Thomas Kropf, George Logothetis
    Verifying Imprecisely Working Arithmetic Circuits. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:65-0 [Conf]
  11. Ralf Reetz, Klaus Schneider, Thomas Kropf
    Formal Specification in VHDL for Hardware Verification. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:257-0 [Conf]
  12. Jürgen Ruf, Dirk W. Hoffmann, Joachim Gerlach, Thomas Kropf, Wolfgang Rosenstiel, Wolfgang Müller 0003
    The simulation semantics of systemC. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:64-70 [Conf]
  13. Jürgen Ruf, Dirk W. Hoffmann, Thomas Kropf, Wolfgang Rosenstiel
    Simulation-guided property checking based on a multi-valued AR-automata. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:742-748 [Conf]
  14. Jürgen Ruf, Thomas Kropf
    Analyzing Real-Time Systems. [Citation Graph (0, 0)][DBLP]
    DATE, 2000, pp:243-0 [Conf]
  15. Jürgen Ruf, Roland J. Weiss, Thomas Kropf, Wolfgang Rosenstiel
    Modeling and Formal Verification of Production Automation Systems. [Citation Graph (0, 0)][DBLP]
    SoftSpez Final Report, 2004, pp:541-566 [Conf]
  16. Jürgen Ruf, Thomas Kropf
    Formal Data Analysis of Timed Finite State Systems. [Citation Graph (0, 0)][DBLP]
    ECRTS, 2002, pp:257-0 [Conf]
  17. Klaus Schneider, Thomas Kropf, Ramayya Kumar
    Control Path Oriented Verification of Sequential Generic Circuits with Control and Data Path. [Citation Graph (0, 0)][DBLP]
    EDAC-ETC-EUROASIC, 1994, pp:648-652 [Conf]
  18. Jürgen Frößl, Thomas Kropf
    A New Model to Uniformly Represent the Function and Timing of MOS Circuits and its Application to VHDL Simulation. [Citation Graph (0, 0)][DBLP]
    EDAC-ETC-EUROASIC, 1994, pp:343-348 [Conf]
  19. Oliver F. Haberl, Thomas Kropf
    Self Testable Boards with Standard IEEE 1149.5 Module Test and Maintenance (MTM) Bus Interface. [Citation Graph (0, 0)][DBLP]
    EDAC-ETC-EUROASIC, 1994, pp:220-225 [Conf]
  20. Dirk W. Hoffmann, Thomas Kropf
    Can Automatic Design Error Correction be Applied to Large Circuits? [Citation Graph (0, 0)][DBLP]
    EUROMICRO, 2000, pp:1114-1121 [Conf]
  21. Dirk W. Hoffmann, Jürgen Ruf, Thomas Kropf, Wolfgang Rosenstiel
    Simulation Meets Verification: Checking Temporal Properties in SystemC. [Citation Graph (0, 0)][DBLP]
    EUROMICRO, 2000, pp:1435-0 [Conf]
  22. Thomas Kropf
    Appendix: The Common Book Examples. [Citation Graph (0, 0)][DBLP]
    Formal Hardware Verification, 1997, pp:330-367 [Conf]
  23. Klaus Schneider, Thomas Kropf
    The C@S System. [Citation Graph (0, 0)][DBLP]
    Formal Hardware Verification, 1997, pp:248-329 [Conf]
  24. Jürgen Ruf, Thomas Kropf
    Using MTBDDs for Compostion and Model Checking of Real-Time Systems. [Citation Graph (0, 0)][DBLP]
    FMCAD, 1998, pp:185-202 [Conf]
  25. Klaus Schneider, Thomas Kropf
    A Unified Approach for Combining Different Formalisms for Hardware Verification. [Citation Graph (0, 0)][DBLP]
    FMCAD, 1996, pp:202-217 [Conf]
  26. Jürgen Ruf, Thomas Kropf
    A New Algorithm for Discrete Timed Symbolic Model Checking. [Citation Graph (0, 0)][DBLP]
    HART, 1997, pp:18-32 [Conf]
  27. Dirk W. Hoffmann, Thomas Kropf
    Efficient Design Error Correction of Digital Circuits. [Citation Graph (0, 0)][DBLP]
    ICCD, 2000, pp:465-472 [Conf]
  28. Dirk W. Hoffmann, Thomas Kropf
    Automatic Error Correction of Tri-State Circuits. [Citation Graph (0, 0)][DBLP]
    ICCD, 1999, pp:51-0 [Conf]
  29. Jürgen Ruf, Thomas Kropf, Jochen Klose
    A Visual Approach to Validating System Level Designs. [Citation Graph (0, 0)][DBLP]
    ISSS, 2002, pp:186-191 [Conf]
  30. Djones Lettnin, Markus Winterholer, Axel G. Braun, Joachim Gerlach, Jürgen Ruf, Thomas Kropf, Wolfgang Rosenstiel
    Coverage Driven Verification applied to Embedded Software. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:159-164 [Conf]
  31. Oliver F. Haberl, Thomas Kropf
    HIST: A Methodology for the Automatic Insertion of a Hierarchical Self Test. [Citation Graph (0, 0)][DBLP]
    ITC, 1992, pp:732-741 [Conf]
  32. Thomas Kropf, Hans-Joachim Wunderlich
    A Common Approach to Test Generation and Hardware Verification Based on Temporal Logic. [Citation Graph (0, 0)][DBLP]
    ITC, 1991, pp:57-66 [Conf]
  33. Thomas Kropf
    Benchmark-Circuits for Hardware-Verification. [Citation Graph (0, 0)][DBLP]
    TPCD, 1994, pp:1-12 [Conf]
  34. Thomas Kropf, Klaus Schneider, Ramayya Kumar
    A Formal Framework for High Level Synthesis. [Citation Graph (0, 0)][DBLP]
    TPCD, 1994, pp:223-238 [Conf]
  35. Thomas Kropf
    Recent Advancements in Hardware Verification - How to Make Theorem Proving Fit for an Industrial Usage. [Citation Graph (0, 0)][DBLP]
    TPHOLs, 1999, pp:1-4 [Conf]
  36. Ramayya Kumar, Thomas Kropf, Klaus Schneider
    Integrating a First-Order Automatic Prover in the HOL Environment. [Citation Graph (0, 0)][DBLP]
    TPHOLs, 1991, pp:170-176 [Conf]
  37. Ramayya Kumar, Thomas Kropf, Klaus Schneider
    First Steps Towards Automating Hardware Proofs in HOL. [Citation Graph (0, 0)][DBLP]
    TPHOLs, 1991, pp:190-193 [Conf]
  38. Klaus Schneider, Ramayya Kumar, Thomas Kropf
    Efficient Representation and Computation of Tableau Proofs. [Citation Graph (0, 0)][DBLP]
    TPHOLs, 1992, pp:39-57 [Conf]
  39. Klaus Schneider, Ramayya Kumar, Thomas Kropf
    Modelling Generic Hardware Structures by Abstract Datatypes. [Citation Graph (0, 0)][DBLP]
    TPHOLs, 1992, pp:165-175 [Conf]
  40. Klaus Schneider, Ramayya Kumar, Thomas Kropf
    Alternative Proof Procedures for Finite-State Machines in Higher-Order Logic. [Citation Graph (0, 0)][DBLP]
    HUG, 1993, pp:213-226 [Conf]
  41. Klaus Schneider, Ramayya Kumar, Thomas Kropf
    Eliminating Higher-Order Quantifiers to Obtain Decision Procedures for Hardware Verification. [Citation Graph (0, 0)][DBLP]
    HUG, 1993, pp:385-398 [Conf]
  42. Klaus Schneider, Ramayya Kumar, Thomas Kropf
    Automating Verification by Functional Abstraction at the System Level. [Citation Graph (0, 0)][DBLP]
    TPHOLs, 1994, pp:391-406 [Conf]
  43. Ralf Reetz, Thomas Kropf
    Simplifying Deep Embedding: A Formalised Code Generator. [Citation Graph (0, 0)][DBLP]
    TPHOLs, 1994, pp:378-390 [Conf]
  44. Klaus Schneider, Ramayya Kumar, Thomas Kropf
    Structurein Hardware Proofs: Fist Steps Towards Automation in a Higher-Order Environment. [Citation Graph (0, 0)][DBLP]
    VLSI, 1991, pp:81-90 [Conf]
  45. Ramayya Kumar, Thomas Kropf, Klaus Schneider
    Formal synthesis of circuits with a simple handshake protocol. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1995, pp:255-259 [Conf]
  46. Pradeep K. Nalla, Roland J. Weiss, Prakash M. Peranandam, Jürgen Ruf, Thomas Kropf, Wolfgang Rosenstiel
    Distributed Symbolic Bounded Property Checking. [Citation Graph (0, 0)][DBLP]
    Electr. Notes Theor. Comput. Sci., 2006, v:135, n:2, pp:47-63 [Journal]
  47. Jürgen Ruf, Thomas Kropf
    Symbolic Verification and Analysis of Discrete Timed Systems. [Citation Graph (0, 0)][DBLP]
    Formal Methods in System Design, 2003, v:23, n:1, pp:67-108 [Journal]
  48. Klaus Schneider, Ramayya Kumar, Thomas Kropf
    Accelerating Tableaux Proofs Using Compact Representations. [Citation Graph (0, 0)][DBLP]
    Formal Methods in System Design, 1994, v:5, n:1/2, pp:145-176 [Journal]
  49. Ramayya Kumar, Klaus Schneider, Thomas Kropf
    Structuring and Automating Hardware Proofs in a Higher-Order Theorem-Proving Environment. [Citation Graph (0, 0)][DBLP]
    Formal Methods in System Design, 1993, v:2, n:2, pp:165-223 [Journal]
  50. Ralf Reetz, Thomas Kropf
    A Flowgraph Semantics of VHDL: Toward a VHDL Verification Workbench in HOL. [Citation Graph (0, 0)][DBLP]
    Formal Methods in System Design, 1995, v:7, n:1/2, pp:73-99 [Journal]
  51. Thomas Kropf
    Software Bugs Seen from an Industrial Perspective or Can Formal Methods Help on Automotive Software Development? [Citation Graph (0, 0)][DBLP]
    CAV, 2007, pp:3- [Conf]

  52. Verification of Temporal Properties in Automotive Embedded Software. [Citation Graph (, )][DBLP]


  53. Using MTBDDs for discrete timed symbolic model checking. [Citation Graph (, )][DBLP]


  54. Semiformal verification of temporal properties in automotive hardware dependent software. [Citation Graph (, )][DBLP]


  55. Towards assertion-based verification of heterogeneous system designs. [Citation Graph (, )][DBLP]


  56. Linking Functional Requirements and Software Verification. [Citation Graph (, )][DBLP]


  57. Grid Based Fast Falsification For Bounded Property Checking. [Citation Graph (, )][DBLP]


  58. Efficient and Customizable Integration of Temporal Properties. [Citation Graph (, )][DBLP]


  59. Using Symbolic Simulation for Bounded Property Checking. [Citation Graph (, )][DBLP]


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