Conferences in DBLP
James Armstrong , Chang Cho , Sandeep Shah , Chakravarthy Kosaraju The VHDL Validation Suite. [Citation Graph (0, 0)][DBLP ] Conf ] Nagisa Ishiura , Hiroto Yasuura , Shuzo Yajima NES: The Behavioral Model for the Formal Semantics of a Hardware Design Language UDL/I. [Citation Graph (0, 0)][DBLP ] Conf ] Nikil D. Dutt , Tedd Hadley , Daniel Gajski An Intermediate Representation for Behavioral Synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Ralph-Michael Kling , Prithviraj Banerjee Optimization by Simulated Evolution with Applications to Standard Cell Placement. [Citation Graph (0, 0)][DBLP ] Conf ] Youssef Saab , Vasant B. Rao Stochastic Evolution: a Fast Effective Heuristic for Some Generic Layout Problems. [Citation Graph (0, 0)][DBLP ] Conf ] Michael Upton , Khosrow Samii , Stephen Sugiyama Integrated Placement for Mixed Macro Cell and Standard Cell Designs. [Citation Graph (0, 0)][DBLP ] Conf ] Abhijit Chatterjee , Richard I. Hartley A New Simultaneous Circuit Partitioning and Chip Placement Approach Based on Simulated Annealing. [Citation Graph (0, 0)][DBLP ] Conf ] Karl S. Brace , Richard L. Rudell , Randal E. Bryant Efficient Implementation of a BDD Package. [Citation Graph (0, 0)][DBLP ] Conf ] Jerry R. Burch , Edmund M. Clarke , Kenneth L. McMillan , David L. Dill Sequential Circuit Verification Using Symbolic Model Checking. [Citation Graph (0, 0)][DBLP ] Conf ] Shin-ichi Minato , Nagisa Ishiura , Shuzo Yajima Shared Binary Decision Diagram with Attributed Edges for Efficient Boolean function Manipulation. [Citation Graph (1, 0)][DBLP ] Conf ] Petra Michel Women in the Microelectronics Industry (Panel Abstract). [Citation Graph (0, 0)][DBLP ] Conf ] David C. Ku , Giovanni De Micheli Relative Scheduling Under Timing Constraints. [Citation Graph (0, 0)][DBLP ] Conf ] Cheng-Tsung Hwang , Yu-Chin Hsu , Youn-Long Lin Optimum and Heuristic Data Path Scheduling Under Resource Constraints. [Citation Graph (0, 0)][DBLP ] Conf ] Richard J. Cloutier , Donald E. Thomas The Combination of Scheduling, Allocation, and Mapping in a Single Algorithm. [Citation Graph (0, 0)][DBLP ] Conf ] Christos A. Papachristou , Haluk Konuk A Linear Program Driven Scheduling and Allocation Method Followed by an Interconnect Optimization Algorithm. [Citation Graph (0, 0)][DBLP ] Conf ] Wilm E. Donath , Reini J. Norman , Bhuwan K. Agrawal , Stephen E. Bello , Sang-Yong Han , Jerome M. Kurtzberg , Paul Lowy , Roger I. McMillan Timing Driven Placement Using Complete Path Delays. [Citation Graph (0, 0)][DBLP ] Conf ] Suphachai Sutanthavibul , Eugene Shragowitz An Adaptive Timing-Driven Layout for High Speed VLSI. [Citation Graph (0, 0)][DBLP ] Conf ] Masayuki Terai , Kazuhiro Takahashi , Koji Sato A New Min-Cut Placement Algorithm for Timing Assurance Layout Design Meeting Net Length Constraint. [Citation Graph (0, 0)][DBLP ] Conf ] Ichiang Lin , David Hung-Chang Du Performance-Driven Constructive Placement. [Citation Graph (0, 0)][DBLP ] Conf ] Daniel R. Brasen , Michael L. Bushnell MHERTZ: A New Optimization Algorithm for Floorplanning and Global Routing. [Citation Graph (0, 0)][DBLP ] Conf ] Karem A. Sakallah , Trevor N. Mudge , Kunle Olukotun Analysis and Design of Latch-Controlled Synchronous Digital Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Alan R. Martello , Steven P. Levitan , Donald M. Chiarulli Timing Verification Using HDTV. [Citation Graph (0, 0)][DBLP ] Conf ] Patrick C. McGeer , Robert K. Brayton Timing Analysis in Precharge/Unate Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Nagisa Ishiura , Yutaka Deguchi , Shuzo Yajima Coded Time-Symbolic Simulation Using Shared Binary Decision Diagram. [Citation Graph (0, 0)][DBLP ] Conf ] Andrea Casotto , A. Richard Newton , Alberto L. Sangiovanni-Vincentelli Design Management Based on Design Traces. [Citation Graph (0, 0)][DBLP ] Conf ] Pieter van der Wolf , G. W. Sloof , Peter Bingley , Patrick Dewilde Meta Data Management in the NELSIS CAD Framework. [Citation Graph (0, 0)][DBLP ] Conf ] Gwo-Dong Chen , Daniel Gajski An Intelligent Component Database for Behavioral Synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Lung-Chun Liu Design Data Management in a CAD Framework Environment. [Citation Graph (0, 0)][DBLP ] Conf ] Douglas M. Grant , Peter B. Denyer Memory, Control and Communications Synthesis for Scheduled Algorithms. [Citation Graph (0, 0)][DBLP ] Conf ] Tai A. Ly , W. Lloyd Elwood , Emil F. Girczyc A Generalized Interconnect Model for Data Path Synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Kristen N. McNall , Albert E. Casavant Automatic Operator Configuration in the Synthesis of Pipelined Architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Ting-Chi Wang , D. F. Wong An Optimal Algorithm for Floorplan Area Optimization. [Citation Graph (0, 0)][DBLP ] Conf ] Suphachai Sutanthavibul , Eugene Shragowitz , J. Ben Rosen An Analytical Approach to Floorplan Design and Optimization. [Citation Graph (0, 0)][DBLP ] Conf ] Deborah C. Wang Pad Placement and Ring Routing for Custom Chip Layout. [Citation Graph (0, 0)][DBLP ] Conf ] Mike Spreitzer Comparing Structurally Different Views of a VLSI Design. [Citation Graph (0, 0)][DBLP ] Conf ] Abhijit Ghosh , Srinivas Devadas , A. Richard Newton Verification of Interacting Sequential Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Basant R. Chawla Distributed Computing Environment for Design Automation in the 90's (Panel Abstract). [Citation Graph (0, 0)][DBLP ] Conf ] Srinivas Devadas , Kurt Keutzer Synthesis and Optimization Procedures for Robustly Delay-Fault Testable Combinational Logic Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Kurt Keutzer , Sharad Malik , Alexander Saldanha Is Redundancy Necessary to Reduce Delay. [Citation Graph (0, 0)][DBLP ] Conf ] Vishwani D. Agrawal , Kwang-Ting Cheng Test Function Specification in Synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Antun Domic Layout Synthesis of MOS Digital Cells. [Citation Graph (0, 0)][DBLP ] Conf ] Goro Suzuki , Yoshio Okamura A Practical Online Design Rule Checking System. [Citation Graph (0, 0)][DBLP ] Conf ] Erik C. Carlson , Rob A. Rutenbar Design and Performance Evaluation of New Massively Parallel VLSI Mask Verification Algorithms in JIGSAW. [Citation Graph (0, 0)][DBLP ] Conf ] Bruce A. Tonkin Circuit Extraction on a Message-Based Multiprocessor. [Citation Graph (0, 0)][DBLP ] Conf ] Timothy J. Barnes SKILL: A CAD System Extension Language. [Citation Graph (0, 0)][DBLP ] Conf ] Marwan A. Jabri BREL - a Prolog Knowledge-based System Shell for VLSI CAD. [Citation Graph (0, 0)][DBLP ] Conf ] Kenneth W. Fiduk , Sally Kleinfeldt , Marta Kosarchyn , Eileen B. Perez Design Methodology Management - a CAD Framework Initiative Perspective. [Citation Graph (0, 0)][DBLP ] Conf ] Hitomi Sato , Yoshihiro Yasue , Yusuke Matsunaga , Masahiro Fujita Boolean Resubstitution with Permissible Functions and Binary Decision Diagrams. [Citation Graph (0, 0)][DBLP ] Conf ] Abdul A. Malik , Robert K. Brayton , A. Richard Newton , Alberto L. Sangiovanni-Vincentelli Reduced Offsets for Two-Level Multi-Valued Logic Minimization. [Citation Graph (0, 0)][DBLP ] Conf ] Hamid Savoj , Robert K. Brayton The Use of Observability and External Don't Cares for the Simplification of Multi-Level Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Kwang-Ting Cheng , Vishwani D. Agrawal An Entropy Measure for the Complexity of Multi-Output Boolean Functions. [Citation Graph (0, 0)][DBLP ] Conf ] H. Cai , Stefaan Note , Paul Six , Hugo De Man A Data Path Layout Assembler for High Performance DSP Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Dwight D. Hill , Don Shugard Global Routing Considerations in a Cell Synthesis System. [Citation Graph (0, 0)][DBLP ] Conf ] Dwight D. Hill , Bryan Preas Benchmarks for Cell Synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Tsuneo Okubo , Takashi Watanabe , Kou Wada New Algorithm for Overlapping Cell Treatment in Hierarchical CAD Data/Electron Beam Exposure Data Conversion. [Citation Graph (0, 0)][DBLP ] Conf ] Chin-Long Wey , Jyhyeung Ding , Tsin-Yuan Chang Design of Repairable and Fully Diagnosable Folded PLAs for Yield Enhancement. [Citation Graph (0, 0)][DBLP ] Conf ] D. David Forsythe , Atul P. Agarwal , Chune-Sin Yeh , Sheldon Aronowitz , Bhaskar Gadepally NASFLOW, a Simulation Tool for Silicon Technology Development. [Citation Graph (0, 0)][DBLP ] Conf ] Alberto L. Sangiovanni-Vincentelli Testing Strategies for the 1990's (Panel Abstract). [Citation Graph (0, 0)][DBLP ] Conf ] Kuang-Chien Chen , Saburo Muroga Timing Optimization for Multi-Level Combinational Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Naohiro Kageyama , Chihei Miura , Tsuguo Shimizu Logic Optimization Algorithm by Linear Programming Approach. [Citation Graph (0, 0)][DBLP ] Conf ] Shen Lin , Malgorzata Marek-Sadowska , Ernest S. Kuh Delay and Area Optimization in Standard-Cell Design. [Citation Graph (0, 0)][DBLP ] Conf ] Pak K. Chan Algorithms for Library-Specific Sizing of Combinational Logic. [Citation Graph (0, 0)][DBLP ] Conf ] Kanwar Jit Singh , Alberto L. Sangiovanni-Vincentelli A Heuristic Algorithm for the Fanout Problem. [Citation Graph (0, 0)][DBLP ] Conf ] John P. Fishburn A Depth-Decreasing Heuristic for Combinational Logic: Or How To Convert a Ripple-Carry Adder Into A Carry-Lookahead Adder Or Anything in-between. [Citation Graph (0, 0)][DBLP ] Conf ] Pierre Abouzeid , K. Sakouti , Gabriele Saucier , F. Poirot Multilevel Synthesis Minimizing the Routing Factor. [Citation Graph (0, 0)][DBLP ] Conf ] Akira Onozawa Layout Compaction with Attractive and Repulsive Constraints. [Citation Graph (0, 0)][DBLP ] Conf ] David Marple A Hierarchy Preserving Hierarchical Compactor. [Citation Graph (0, 0)][DBLP ] Conf ] Chi-Yuan Lo , Ravi Varadarajan An O(n 1.5 logn ) 1-d Compaction Algorithm. [Citation Graph (0, 0)][DBLP ] Conf ] Nobu Matsumoto , Yoko Watanabe , Kimiyoshi Usami , Yukio Sugeno , Hiroshi Hatada , Shojiro Mori Datapath Generator Based on Gate-Level Symbolic Layout. [Citation Graph (0, 0)][DBLP ] Conf ] Gih-Guang Hung , Yen-Cheng Wen , Kyle Gallivan , Resve A. Saleh Parallel Circuit Simulation Using Hierarchical Relaxation. [Citation Graph (0, 0)][DBLP ] Conf ] Gung-Chung Yang PARASPICE: A Parallel Circuit Simulator for Shared-Memory Multiprocessors. [Citation Graph (0, 0)][DBLP ] Conf ] Steven Paul McCormick , Jonathan Allen Waveform Moment Methods for Improved Interconnection Analysis. [Citation Graph (0, 0)][DBLP ] Conf ] K. Adamiak , R. Allen , J. Poltz , C. Rebizant , A. Wexler System Simulation of Printed Circuit Boards Including Packages and Connectors. [Citation Graph (0, 0)][DBLP ] Conf ] Wayne Bower , Carl Seaquist , Wayne Wolf A Framework for Industrial Layout Generators. [Citation Graph (0, 0)][DBLP ] Conf ] Jiri Soukup Organized C: A Unified Method of Handling Data in CAD Algorithms and Databases. [Citation Graph (0, 0)][DBLP ] Conf ] Moon-Jung Chung , Sangchul Kim An Object-Oriented VHDL Design Environment. [Citation Graph (0, 0)][DBLP ] Conf ] S. J. Feghhi , Michael M. Marefat , Rangasami L. Kashyap An Object-Oriented Kernel for an Integrated Design and Process Planning System. [Citation Graph (0, 0)][DBLP ] Conf ] Roni Potasman , Joseph Lis , Alexandru Nicolau , Daniel Gajski Percolation Based Synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Raul Compasano , Reinaldo A. Bergamaschi Synthesis Using Path-Based scheduling: algorithms and Exercises. [Citation Graph (0, 0)][DBLP ] Conf ] Josef Scheichenzuber , Werner Grass , Ulrich Lauther , Sabine März Global Hardware Synthesis from Behavioral Dataflow Descriptions. [Citation Graph (0, 0)][DBLP ] Conf ] Uminder Singh , C. Y. Roger Chen A Transistor Reordering Technique for Gate Matrix Layout. [Citation Graph (0, 0)][DBLP ] Conf ] Knut M. Just , Edgar Auer , Werner L. Schiele , Alexander Schwaferts PALACE: A Kayout Generator for SCVS Logic Blocks. [Citation Graph (0, 0)][DBLP ] Conf ] Yung-Ching Hsieh , Chi-Yi Hwang , Youn-Long Lin , Yu-Chin Hsu LiB: A Cell Layout Generator. [Citation Graph (0, 0)][DBLP ] Conf ] Peter M. Maurer , Zhicheng Wang Techniques for Unit-Delay Compiled Simulation. [Citation Graph (0, 0)][DBLP ] Conf ] K. Subramanian , Mehdi R. Zargham Distributed and Parallel Demand Driven Logic Simulation. [Citation Graph (0, 0)][DBLP ] Conf ] Zhicheng Wang , Peter M. Maurer LECSIM: A Levelized Event Driven Compiled Logic Simulation. [Citation Graph (0, 0)][DBLP ] Conf ] A. Richard Newton Standards, Openness and Design Environments in Electronic Design Automation (Panel Abstract). [Citation Graph (0, 0)][DBLP ] Conf ] Chu-Yi Huang , Yen-Shen Chen , Youn-Long Lin , Yu-Chin Hsu Data Path Allocation Based on Bipartite Weighted Matching. [Citation Graph (0, 0)][DBLP ] Conf ] Nam Sung Woo A Global, Dynamic Register Allocation and Binding for a Data Path Synthesis System. [Citation Graph (0, 0)][DBLP ] Conf ] Kayhan Küçükçakar , Alice C. Parker Data Path Tradeoffs Using MABAL. [Citation Graph (0, 0)][DBLP ] Conf ] Randal E. Bryant Symbolic Simulation - Techniques and Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Eun Sei Park , M. Ray Mercer An Efficient Delay Test Generation System for Combinational Logic Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Noriyuki Ito Automatic Incorporation of On-Chip Testability Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Thomas M. Niermann , Wu-Tung Cheng , Janak H. Patel Proofs: A Fast, Memory Efficient Sequential Circuit Fault Simulator. [Citation Graph (0, 0)][DBLP ] Conf ] William Lattin Integration of Hardware and Software in Embedded Systems Design (Panel Abstract). [Citation Graph (0, 0)][DBLP ] Conf ] Mauricio Breternitz Jr. , John Paul Shen Architecture Synthesis of High-Performance Application-Specific Processors. [Citation Graph (0, 0)][DBLP ] Conf ] Robin C. Sarma , Mark D. Dooley , N. Craig Newman , Graham Hetherington High-Level Synthesis: Technology Transfer to Industry. [Citation Graph (0, 0)][DBLP ] Conf ] Patrick Edmond , Anurag P. Gupta , Daniel P. Siewiorek , Audrey A. Brennan ASSURE: Automated Design for Dependability. [Citation Graph (0, 0)][DBLP ] Conf ] Umakanta Choudhury , Alberto L. Sangiovanni-Vincentelli Constraint Generation for Routing Analog Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Jonathan W. Greene , Vwani P. Roychowdhury , Sinan Kaptanoglu , Abbas El Gamal Segmented Channel Routing. [Citation Graph (0, 0)][DBLP ] Conf ] Michael A. B. Jackson , Arvind Srinivasan , Ernest S. Kuh Clock Routing for High-Performance ICs. [Citation Graph (0, 0)][DBLP ] Conf ] Abhijit Ghosh , Srinivas Devadas , A. Richard Newton Sequential Test Generation at the Register-Transfer and Logic Levels. [Citation Graph (0, 0)][DBLP ] Conf ] P. C. Ward , James R. Armstrong Behavioral Fault Simulation in VHDL. [Citation Graph (0, 0)][DBLP ] Conf ] Ramachandra P. Kunda , Jacob A. Abraham , Bharat Deep Rathi , Prakash Narain Speed Up of Test Generation Using High-Level Primitives. [Citation Graph (0, 0)][DBLP ] Conf ] Kurt Keutzer Impact and Evaluation of Competing Implementation Media for ASIC's (Panel Abstract). [Citation Graph (0, 0)][DBLP ] Conf ] Pranav Ashar , Srinivas Devadas , A. Richard Newton A Unified Approach to the Decomposition and Re-Decomposition of Sequential Machines. [Citation Graph (0, 0)][DBLP ] Conf ] Sujit Dey , Franc Brglez , Gershon Kedem Corolla Based Circuit Partitioning and Resynthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Robert J. Francis , Jonathan Rose , Kevin Chung Chortle: A Technology Mapping Program for Lookup Table-Based Field Programmable Gate Arrays. [Citation Graph (0, 0)][DBLP ] Conf ] Rajeev Murgai , Yoshihito Nishizaki , Narendra V. Shenoy , Robert K. Brayton , Alberto L. Sangiovanni-Vincentelli Logic Synthesis for Programmable Gate Arrays. [Citation Graph (0, 0)][DBLP ] Conf ] Werner L. Schiele , Th. Krüger , Knut M. Just , F. H. Kirsch A Gridless Router for Industrial Design Rules. [Citation Graph (0, 0)][DBLP ] Conf ] Ramin Hojati Layout Optimization by Pattern Modification. [Citation Graph (0, 0)][DBLP ] Conf ] Yang Cai , D. F. Wong A Channel/Switchbox Definition Algorithm for Building-Block Layout. [Citation Graph (0, 0)][DBLP ] Conf ] Masato Edahiro , Takeshi Yoshimura New Placement and Global Routing Algorithms for Standard Cell Layouts. [Citation Graph (0, 0)][DBLP ] Conf ] Masao Sato , Kazuto Kubota , Tatsuo Ohtsuki A Hardware Implementation of Gridless Routing Based on Content Addressable Memory. [Citation Graph (0, 0)][DBLP ] Conf ] Randall J. Brouwer , Prithviraj Banerjee PHIGURE: A Parallel Hierarchical Global Router. [Citation Graph (0, 0)][DBLP ] Conf ] Srimat T. Chakradhar , Vishwani D. Agrawal , Michael L. Bushnell Automatic Test Generation Using Quadratic 0-1 Programming. [Citation Graph (0, 0)][DBLP ] Conf ] Hyung Ki Lee , Dong Sam Ha SOPRANO: An Efficient Automatic Test Pattern Generator for Stuck-Open Faults in CMOS Combinational Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] John Giraldi , Michael L. Bushnell EST: The New Frontier in Automatic Test-Pattern Generation. [Citation Graph (0, 0)][DBLP ] Conf ] Kenneth M. Butler , M. Ray Mercer The Influences of Fault Type and Topology on Fault Model Performance and the Implications to Test and Testable Design. [Citation Graph (0, 0)][DBLP ] Conf ] Tim Andrews Object Databases in Electronic Design: Implementation Experiences (Panel Abstract). [Citation Graph (0, 0)][DBLP ] Conf ] Gregory S. Whitcomb , A. Richard Newton Abstract Data Types and High-Level Synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Ajay J. Daga , William P. Birmingham Failure Recovery in the MICON System. [Citation Graph (0, 0)][DBLP ] Conf ] Wayne Wolf The FSM Network Model for Behavioral Synthesis of Control-Dominated Machines. [Citation Graph (0, 0)][DBLP ] Conf ] Roshan A. Gidwani , Naveed A. Sherwani MISER: An Integrated Three Layer Gridless Channel Router and Compactor. [Citation Graph (0, 0)][DBLP ] Conf ] Evagelos Katsadas , Edwin Kinnen A Multi-Layer Router Utilizing Over-Cell Areas. [Citation Graph (0, 0)][DBLP ] Conf ] Jason Cong , Bryan Preas , C. L. Liu General Models and Algorithms for Over-the-Cell Routing in Standard Cell Design. [Citation Graph (0, 0)][DBLP ] Conf ] Tyh-Song Hwang , Chung-Len Lee , Wen-Zen Shen , Ching Ping Wu A Parallel Pattern Mixed-Level Fault Simulator. [Citation Graph (0, 0)][DBLP ] Conf ] T. Ramakrishnan , L. Kinney Extension of the Critical Path Tracing Algorithm. [Citation Graph (0, 0)][DBLP ] Conf ] Shambhu J. Upadhyaya , John A. Thodiyil BIST PLAs, Pass or Fail - A Case Study. [Citation Graph (0, 0)][DBLP ] Conf ] Weiwei Mao , Michael D. Ciletti A Variable Observation Time Method for Testing Delay Faults. [Citation Graph (0, 0)][DBLP ] Conf ] T. Y. Kuo , J. Y. Lee , J. F. Wang A Fault Analysis Method for Synchronous Sequential Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Sreejit Chakravarty On Synthesizing and Identifying Stuck-Open Testable CMOS Combinational Circuits (extended abstract). [Citation Graph (0, 0)][DBLP ] Conf ] 