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A. Richard Newton :
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Naji Ghazal , A. Richard Newton , Jan M. Rabaey Retargetable estimation scheme for DSP architecture selection. [Citation Graph (0, 0)][DBLP ] ASP-DAC, 2000, pp:485-490 [Conf ] Kenneth H. Keller , A. Richard Newton KIC2: A Low-Cost, Interactive Editor for Integrated Circuit Design. [Citation Graph (0, 0)][DBLP ] COMPCON, 1982, pp:305-306 [Conf ] Pranav Ashar , Srinivas Devadas , A. Richard Newton A Unified Approach to the Decomposition and Re-Decomposition of Sequential Machines. [Citation Graph (0, 0)][DBLP ] DAC, 1990, pp:601-606 [Conf ] Francis L. Chan , Mark D. Spiller , A. Richard Newton WELD - An Environment for Web-based Electronic Design. [Citation Graph (0, 0)][DBLP ] DAC, 1998, pp:146-151 [Conf ] Andrea Casotto , A. Richard Newton , Alberto L. Sangiovanni-Vincentelli Design Management Based on Design Traces. [Citation Graph (0, 0)][DBLP ] DAC, 1990, pp:136-141 [Conf ] Srinivas Devadas , Hi-Keung Tony Ma , A. Richard Newton On the Verification of Sequential Machines at Differing Levels of Abstraction. [Citation Graph (0, 0)][DBLP ] DAC, 1987, pp:271-276 [Conf ] Srinivas Devadas , A. Richard Newton GENIE: a generalized array optimizer for VLSI synthesis. [Citation Graph (0, 0)][DBLP ] DAC, 1986, pp:631-637 [Conf ] Naji Ghazal , A. Richard Newton , Jan M. Rabaey Predicting performance potential of modern DSPs. [Citation Graph (0, 0)][DBLP ] DAC, 2000, pp:332-335 [Conf ] Abhijit Ghosh , Srinivas Devadas , A. Richard Newton Verification of Interacting Sequential Circuits. [Citation Graph (0, 0)][DBLP ] DAC, 1990, pp:213-219 [Conf ] Abhijit Ghosh , Srinivas Devadas , A. Richard Newton Sequential Test Generation at the Register-Transfer and Logic Levels. [Citation Graph (0, 0)][DBLP ] DAC, 1990, pp:580-586 [Conf ] Seung Ho Hwang , Young hwan Kim , A. Richard Newton An accuration delay modeling technique for switch-level timing verification. [Citation Graph (0, 0)][DBLP ] DAC, 1986, pp:227-233 [Conf ] George K. Jacob , A. Richard Newton , Donald O. Pederson An empirical analysis of the performance of a multiprocessor-based circuit simulator. [Citation Graph (0, 0)][DBLP ] DAC, 1986, pp:588-593 [Conf ] B. Lin , A. Richard Newton KAHLUA: A Hierarchical Circuit Disassembler. [Citation Graph (0, 0)][DBLP ] DAC, 1987, pp:311-317 [Conf ] Abdul A. Malik , Robert K. Brayton , A. Richard Newton , Alberto L. Sangiovanni-Vincentelli Reduced Offsets for Two-Level Multi-Valued Logic Minimization. [Citation Graph (0, 0)][DBLP ] DAC, 1990, pp:290-296 [Conf ] A. Richard Newton Twenty-Five Years of Electronic Design Automation. [Citation Graph (0, 0)][DBLP ] DAC, 1988, pp:2- [Conf ] A. Richard Newton Standards, Openness and Design Environments in Electronic Design Automation (Panel Abstract). [Citation Graph (0, 0)][DBLP ] DAC, 1990, pp:497-498 [Conf ] A. Richard Newton Framework Standards: How Important are They? (Panel Abstract). [Citation Graph (0, 0)][DBLP ] DAC, 1991, pp:315- [Conf ] A. Richard Newton Technical Challenges of IP and System-on-Chip: The ASIC Vendor Perspective (Panel). [Citation Graph (0, 0)][DBLP ] DAC, 1998, pp:501- [Conf ] A. Richard Newton , Walden C. Rhines , Sünke Mehrgardt , Henry Samueli , Tudor Brown Embedded systems design in the new millennium (panel session). [Citation Graph (0, 0)][DBLP ] DAC, 2000, pp:338-339 [Conf ] Jaijeet S. Roychowdhury , A. Richard Newton , Donald O. Pederson Simulating Lossy Interconnect with High Frequency Nonidealities in Linear Time. [Citation Graph (0, 0)][DBLP ] DAC, 1992, pp:75-80 [Conf ] Abdallah Tabbara , Robert K. Brayton , A. Richard Newton Retiming for DSM with Area-Delay Trade-Offs and Delay Constraints. [Citation Graph (0, 0)][DBLP ] DAC, 1999, pp:725-730 [Conf ] Gregory S. Whitcomb , A. Richard Newton Abstract Data Types and High-Level Synthesis. [Citation Graph (0, 0)][DBLP ] DAC, 1990, pp:680-685 [Conf ] James Shin Young , Josh MacDonald , Michael Shilman , Abdallah Tabbara , Paul N. Hilfinger , A. Richard Newton Design and Specification of Embedded Systems in Java Using Successive, Formal Refinement. [Citation Graph (0, 0)][DBLP ] DAC, 1998, pp:70-75 [Conf ] A. Richard Newton Great works for the 21st century: a critical role for the modern research university. [Citation Graph (0, 0)][DBLP ] EMSOFT, 2004, pp:1- [Conf ] Carlo H. Séquin , A. Richard Newton , Alberto L. Sangiovanni-Vincentelli Highlights of VLSI Research at Berkeley. [Citation Graph (0, 0)][DBLP ] FJCC, 1986, pp:894-897 [Conf ] Pranav Ashar , Abhijit Ghosh , Srinivas Devadas , A. Richard Newton Implicit State Transition Graphs: Applications to Sequential Logic Synthesis and Test. [Citation Graph (0, 0)][DBLP ] ICCAD, 1990, pp:84-87 [Conf ] Premal Buch , Amit Narayan , A. Richard Newton , Alberto L. Sangiovanni-Vincentelli Logic synthesis for large pass transistor circuits. [Citation Graph (0, 0)][DBLP ] ICCAD, 1997, pp:663-670 [Conf ] Wray L. Buntine , Lixin Su , A. Richard Newton , Andrew Mayer Adaptive methods for netlist partitioning. [Citation Graph (0, 0)][DBLP ] ICCAD, 1997, pp:356-363 [Conf ] Chuck Kring , A. Richard Newton A Cell-Replicating Approach to Minicut-Based Circuit Partitioning. [Citation Graph (0, 0)][DBLP ] ICCAD, 1991, pp:2-5 [Conf ] Bill Lin , Hervé J. Touati , A. Richard Newton Don't Care Minimization of Multi-Level Sequential Logic Networks. [Citation Graph (0, 0)][DBLP ] ICCAD, 1990, pp:414-417 [Conf ] Jaijeet S. Roychowdhury , A. Richard Newton , Donald O. Pederson An Impulse-Response Based Linear Time-Complexity Algorithm for Lossy Interconnect Simulation. [Citation Graph (0, 0)][DBLP ] ICCAD, 1991, pp:62-65 [Conf ] Mark D. Spiller , A. Richard Newton EDA and the network. [Citation Graph (0, 0)][DBLP ] ICCAD, 1997, pp:470-476 [Conf ] Kurt Keutzer , Sharad Malik , A. Richard Newton From ASIC to ASIP: The Next Design Discontinuity. [Citation Graph (0, 0)][DBLP ] ICCD, 2002, pp:84-90 [Conf ] Kurt Keutzer , A. Richard Newton The MARCO/DARPA Gigascale Silicon Research Center. [Citation Graph (0, 0)][DBLP ] ICCD, 1999, pp:14-0 [Conf ] Bill Lin , A. Richard Newton Implicit Manipulation of Equivalence Classes Using Binary Decision Diagrams. [Citation Graph (0, 0)][DBLP ] ICCD, 1991, pp:81-85 [Conf ] Heloise Hwawen Hse , A. Richard Newton Sketched Symbol Recognition using Zernike Moments. [Citation Graph (0, 0)][DBLP ] ICPR (1), 2004, pp:367-370 [Conf ] Zile Wei , Yu Cao , A. Richard Newton Digital Image Restoration by Exposure-Splitting and Registration. [Citation Graph (0, 0)][DBLP ] ICPR (4), 2004, pp:657-660 [Conf ] Brian W. O'Krafka , A. Richard Newton An Empirical Evaluation of Two Memory-Efficient Directory Methods. [Citation Graph (0, 0)][DBLP ] ISCA, 1990, pp:138-147 [Conf ] Premal Buch , Christopher K. Lennard , A. Richard Newton Engineering change for power optimization using global sensitivity and synthesis flexibility. [Citation Graph (0, 0)][DBLP ] ISLPED, 1997, pp:88-91 [Conf ] Christopher K. Lennard , Premal Buch , A. Richard Newton Logic synthesis using power-sensitive don't care sets. [Citation Graph (0, 0)][DBLP ] ISLPED, 1996, pp:293-296 [Conf ] Christopher K. Lennard , A. Richard Newton An estimation technique to guide low power resynthesis algorithms. [Citation Graph (0, 0)][DBLP ] ISLPD, 1995, pp:227-232 [Conf ] Kurt Keutzer , A. Richard Newton , Narendra V. Shenoy The future of logic synthesis and physical design in deep-submicron process geometries. [Citation Graph (0, 0)][DBLP ] ISPD, 1997, pp:218-224 [Conf ] Zile Wei , Donald Chai , A. Richard Newton , Andreas Kuehlmann Fast Boolean Matching with Don't Cares. [Citation Graph (0, 0)][DBLP ] ISQED, 2006, pp:346-351 [Conf ] Ernst Siepmann , A. Richard Newton TOBAC: A Test Case Browser for Testing Object-Oriented Software. [Citation Graph (0, 0)][DBLP ] ISSTA, 1994, pp:154-168 [Conf ] Srinivas Devadas , Hi-Keung Tony Ma , A. Richard Newton Redundancies and Don't Cares in Sequential Logic Synthesis. [Citation Graph (0, 0)][DBLP ] ITC, 1989, pp:491-500 [Conf ] Srinivas Devadas , Hi-Keung Tony Ma , A. Richard Newton , Alberto L. Sangiovanni-Vincentelli Synthesis and Optimization Procedures for Fully and Easily Testable Sequential Machines. [Citation Graph (0, 0)][DBLP ] ITC, 1988, pp:621-630 [Conf ] Hi-Keung Tony Ma , A. Richard Newton , Srinivas Devadas , Alberto L. Sangiovanni-Vincentelli An Incomplete Scan Design Approach to Test Generation for Sequential Machines. [Citation Graph (0, 0)][DBLP ] ITC, 1988, pp:730-734 [Conf ] Heloise Hwawen Hse , Michael Shilman , A. Richard Newton Robust sketched symbol fragmentation using templates. [Citation Graph (0, 0)][DBLP ] Intelligent User Interfaces, 2004, pp:156-160 [Conf ] Bill Lin , A. Richard Newton Exact Redundant State Registers Removal Based on Binary Decision Diagrams. [Citation Graph (0, 0)][DBLP ] VLSI, 1991, pp:277-286 [Conf ] A. Richard Newton Has CAD for VLSI Reached a Dead End? [Citation Graph (0, 0)][DBLP ] VLSI, 1991, pp:187-192 [Conf ] Heloise Hwawen Hse , A. Richard Newton Recognition and beautification of multi-stroke symbols in digital ink. [Citation Graph (0, 0)][DBLP ] Computers & Graphics, 2005, v:29, n:4, pp:533-546 [Journal ] Juan Bicarregui , D. L. Clutterbuck , Gavin R. Finnie , Howard P. Haughton , Kevin Lano , H. Lesan , D. W. R. M. Marsh , B. M. Matthews , Michael R. Moulding , A. Richard Newton , Brian Ritchie , T. G. A. Rushton , P. N. Scharbach Formal methods into practice: case studies in the application of the B method. [Citation Graph (0, 0)][DBLP ] IEE Proceedings - Software, 1997, v:144, n:2, pp:119-133 [Journal ] Abdallah Tabbara , Bassam Tabbara , Robert K. Brayton , A. Richard Newton Integration of retiming with architectural floorplanning. [Citation Graph (0, 0)][DBLP ] Integration, 2000, v:29, n:1, pp:25-43 [Journal ] Abdul A. Malik , Robert K. Brayton , A. Richard Newton , Alberto L. Sangiovanni-Vincentelli Two-Level Minimization of Multivalued Functions with Large Offsets. [Citation Graph (0, 0)][DBLP ] IEEE Trans. Computers, 1993, v:42, n:11, pp:1325-1342 [Journal ] Pranav Ashar , Srinivas Devadas , A. Richard Newton Optimum and heuristic algorithms for an approach to finite state machine decomposition. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:3, pp:296-310 [Journal ] Pranav Ashar , Srinivas Devadas , A. Richard Newton Irredundant interacting sequential machines via optimal logic synthesis. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:3, pp:311-325 [Journal ] Srinivas Devadas , Hi-Keung Tony Ma , A. Richard Newton On the verification of sequential machines at differing levels of abstraction. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 1988, v:7, n:6, pp:713-722 [Journal ] Srinivas Devadas , Hi-Keung Tony Ma , A. Richard Newton , Alberto L. Sangiovanni-Vincentelli MUSTANG: state assignment of finite state machines targeting multilevel logic implementations. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 1988, v:7, n:12, pp:1290-1300 [Journal ] Srinivas Devadas , Hi-Keung Tony Ma , A. Richard Newton , Alberto L. Sangiovanni-Vincentelli A synthesis and optimization procedure for fully and easily testable sequential machines. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:10, pp:1100-1107 [Journal ] Srinivas Devadas , Hi-Keung Tony Ma , A. Richard Newton , Alberto L. Sangiovanni-Vincentelli Irredundant sequential machines via optimal logic synthesis. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 1990, v:9, n:1, pp:8-18 [Journal ] Srinivas Devadas , A. Richard Newton Topological Optimization of Multiple-Level Array Logic. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 1987, v:6, n:6, pp:915-941 [Journal ] Srinivas Devadas , A. Richard Newton Algorithms for hardware allocation in data path synthesis. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:7, pp:768-781 [Journal ] Srinivas Devadas , A. Richard Newton Decomposition and factorization of sequential finite state machines. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:11, pp:1206-1217 [Journal ] Srinivas Devadas , A. Richard Newton Exact algorithms for output encoding, state assignment, and four-level Boolean minimization. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:1, pp:13-27 [Journal ] Xuejun Du , Gary D. Hachtel , Bill Lin , A. Richard Newton MUSE: a multilevel symbolic encoding algorithm for state assignment. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:1, pp:28-38 [Journal ] Abhijit Ghosh , Srinivas Devadas , A. Richard Newton Test generation and verification for highly sequential circuits. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:5, pp:652-667 [Journal ] Abhijit Ghosh , Srinivas Devadas , A. Richard Newton Heuristic minimization of Boolean relations using testing techniques. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:9, pp:1166-1172 [Journal ] Abhijit Ghosh , Srinivas Devadas , A. Richard Newton Sequential test generation and synthesis for testability at the register-transfer and logic levels. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:5, pp:579-598 [Journal ] Gary D. Hachtel , A. Richard Newton , Alberto L. Sangiovanni-Vincentelli An Algorithm for Optimal PLA Folding. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 1982, v:1, n:2, pp:63-77 [Journal ] Seung Ho Hwang , A. Richard Newton An efficient verifier for finite state machines. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:3, pp:326-334 [Journal ] Kurt Keutzer , A. Richard Newton , Jan M. Rabaey , Alberto L. Sangiovanni-Vincentelli System-level design: orthogonalization of concerns andplatform-based design. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:12, pp:1523-1543 [Journal ] Young hwan Kim , Seung Ho Hwang , A. Richard Newton Electrical-logic simulation and its applications. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:1, pp:8-22 [Journal ] Christopher K. Lennard , A. Richard Newton On estimation accuracy for guiding low-power resynthesis. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:6, pp:644-664 [Journal ] Bill Lin , A. Richard Newton A circuit disassembly technique for synthesizing symbolic layouts from mask descriptions. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 1990, v:9, n:9, pp:959-969 [Journal ] Hi-Keung Tony Ma , Srinivas Devadas , A. Richard Newton , Alberto L. Sangiovanni-Vincentelli Test generation for sequential circuits. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 1988, v:7, n:10, pp:1081-1093 [Journal ] Abdul A. Malik , Robert K. Brayton , A. Richard Newton , Alberto L. Sangiovanni-Vincentelli Reduced offsets for minimization of binary-valued functions. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:4, pp:413-426 [Journal ] Giovanni De Micheli , A. Richard Newton , Alberto L. Sangiovanni-Vincentelli Symmetric Displacement Algorithms for the Timing Analysis of Large Scale Circuits. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 1983, v:2, n:3, pp:167-180 [Journal ] A. Richard Newton , Alberto L. Sangiovanni-Vincentelli Relaxation-Based Electrical Simulation. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 1984, v:3, n:4, pp:308-331 [Journal ] Takayasu Sakurai , Bill Lin , A. Richard Newton Fast simulated diffusion: an optimization algorithm for multiminimum problems and its application to MOSFET model parameter extraction. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:2, pp:228-234 [Journal ] Jaijeet S. Roychowdhury , A. Richard Newton , Donald O. Pederson Algorithms for the transient simulation of lossy interconnect. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:1, pp:96-104 [Journal ] Resve A. Saleh , A. Richard Newton The exploitation of latency and multirate behavior using nonlinear relaxation for circuit simulation. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:12, pp:1286-1298 [Journal ] Lixin Su , Wray L. Buntine , A. Richard Newton , Bradley S. Peters Learning as applied to stochastic optimization for standard-cellplacement. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:4, pp:516-527 [Journal ] Search in 0.030secs, Finished in 0.035secs