Conferences in DBLP
Bhanu Kapoor Low Power Memory Architectures for Video Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Luca Benini , Giovanni De Micheli , Alberto Macii , Enrico Macii , Massimo Poncino Reducing Power Consumption of Dedicated Processors Through Instruction Set Encoding. [Citation Graph (0, 0)][DBLP ] Conf ] A. M. Fahim , Muhammad M. Khellah , Mohamed I. Elmasry A Low-Power High-Performance Embedded SRAM Macrocell. [Citation Graph (0, 0)][DBLP ] Conf ] Amr G. Wassal , M. Anwarul Hasan , Mohamed I. Elmasry Low-Power Design of Finite Field Multipliers for Wireless Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Dusan Suvakovic , C. Andre T. Salama Guidelines for Use of Registers and Multiplexers in Low Power Low Voltage DSP Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Seung-Moon Yoo , Seung-Moon Kang A Bootstrapped NMOS Charge Recovery Logic. [Citation Graph (0, 0)][DBLP ] Conf ] Richard F. Hobson Power Reducing Techniques for Clocked CMOS PLAs. [Citation Graph (0, 0)][DBLP ] Conf ] Yehea I. Ismail , Eby G. Friedman , José Luis Neves Dynamic and Short-Circuit Power of CMOS Gates Driving Lossless Transmission Lines. [Citation Graph (0, 0)][DBLP ] Conf ] Ahmed M. Shams , Magdy A. Bayoumi A New Full Adder Cell for Low-Power Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Victor Varshavsky beta-Driven Threshold Elements. [Citation Graph (0, 0)][DBLP ] Conf ] José G. Delgado-Frias , Jabulani Nyathi A VLSI High-Performance Encoder with Priority Lookahead. [Citation Graph (0, 0)][DBLP ] Conf ] Mayukh Bhattacharya , Pinaki Mazumder Noise Margins of Threshold Logic Gates containing Resonant Tunneling Diodes. [Citation Graph (0, 0)][DBLP ] Conf ] Azman M. Yusof , Lim Chu Aun , S. M. Rezaul Hasan 600 MHz Digitally Controlled BiCMOS Oscillator (DCO) for VLSI Signal Processing & Communication Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Tim Bakken , John Choma Jr. Stability of a Continuous-Time State Variable Filter with OP-AMP and OTA-C Integrators. [Citation Graph (0, 0)][DBLP ] Conf ] I. Thoidis , Dimitrios Soudris , Ioannis Karafyllidis , Adonios Thanailakis , Thanos Stouraitis Multiple-Valued Logic Voltage-Mode Storage Circuits Based On True-Single-Phase Clocked Logic. [Citation Graph (0, 0)][DBLP ] Conf ] João Navarro Jr. , Wilhelmus A. M. Van Noije CMOS Tapered Buffer Design for Small Width Clock/Data Signal Propagation. [Citation Graph (0, 0)][DBLP ] Conf ] Mohamed Nekili , Yvon Savaria , Guy Bois Design of Clock Distribution Networks in Presence of Process Variations. [Citation Graph (0, 0)][DBLP ] Conf ] João Navarro Jr. , Wilhelmus A. M. Van Noije Design of an 8: 1 MUX at 1.7Gbit/s in 0.8?I`m CMOS Technology. [Citation Graph (0, 0)][DBLP ] Conf ] Pranjal Srivastava , Andrew Pua , Larry Welch Issues in the Design of Domino Logic Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Gianluca Giustolisi , Giovanni Palmisano , Gaetano Palumbo , C. Strano A Novel 1.5-V Cmos Mixer. [Citation Graph (0, 0)][DBLP ] Conf ] Can K. Sandalci , Sayfe Kiaei Analysis of Adaptive CMOS Down Conversion Mixers. [Citation Graph (0, 0)][DBLP ] Conf ] Hoda S. Abdel-Aty-Zohdy Artificial Neural Network Electronic Nose for Volatile Organic Compounds. [Citation Graph (0, 0)][DBLP ] Conf ] José G. Delgado-Frias , Richard Diaz A VLSI Self-Compacting Buffer for DAMQ Communication Switches. [Citation Graph (0, 0)][DBLP ] Conf ] Adger E. Harvin III , José G. Delgado-Frias A Dictionary Machine Emulation on a VLSI Computing Tree System. [Citation Graph (0, 0)][DBLP ] Conf ] Ashutosh Kulkarni , Navin Chander , Soumya Pillai , Lizy Kurian John Modeling and Analysis of The Difference-Bit Cache. [Citation Graph (0, 0)][DBLP ] Conf ] Sandeep Agarwal , Fayez El Guibaly Modeling of Shift Register-based ATM Switch. [Citation Graph (0, 0)][DBLP ] Conf ] Jen-Chien Tuan , Chein-Wei Jen An Architecture of Full-Search Block Matching for Minimum Memory Bandwidth Requirement. [Citation Graph (0, 0)][DBLP ] Conf ] Nien-Tsu Wang , Chen-Wei Shih , Duan Juat Wong-Ho , Nam Ling MPEG-2 Video Decoder for DVD. [Citation Graph (0, 0)][DBLP ] Conf ] Eric Senn , Bertrand Zavidovique A Self Timed Asynchronous Router for an Heterogeneous Parallel Machine. [Citation Graph (0, 0)][DBLP ] Conf ] Bassem A. Alhalabi , Qutaibah M. Malluhi , Rafic A. Ayoubi Non-Refreshing Analog Neural Storage Tailored for On-Chip Learning. [Citation Graph (0, 0)][DBLP ] Conf ] Yuke Wang , Xiaoyu Song , El Mostapha Aboulhamid Residue to Binary Number Converters for (2n -1, 2n , 2n +1). [Citation Graph (0, 0)][DBLP ] Conf ] Inseop Lee , W. Kenneth Jenkins The Design of Residue Number System Arithmetic Units for A VLSI Adaptive Equalizer. [Citation Graph (0, 0)][DBLP ] Conf ] Alexander Skavantzos An Efficient Residue to Weighted Converter for a New Residue Number System. [Citation Graph (0, 0)][DBLP ] Conf ] Franco Maloberti , Chen Gang The Chinese Abacus Method: Can We Use It for Digital Arithmetic? [Citation Graph (0, 0)][DBLP ] Conf ] Gwangwoo Choe , Earl E. Swartzlander Jr. Merged Arithmetic for Computing Wavelet Transforms. [Citation Graph (0, 0)][DBLP ] Conf ] Saeid Sadeghi-Emamchaie , Graham A. Jullien , Vassil S. Dimitrov , William C. Miller Digital Arithmetic Using Analog Arrays. [Citation Graph (0, 0)][DBLP ] Conf ] James E. Stine , Michael J. Schulte A Combined Interval and Floating Point Multiplier. [Citation Graph (0, 0)][DBLP ] Conf ] Irith Pomeranz , Sudhakar M. Reddy Test Compaction for Synchronous Sequential Circuits by Test Sequence Recycling. [Citation Graph (0, 0)][DBLP ] Conf ] Rajesh Raina , Robert F. Molyneaux Random Self-Test Method - Applications on PowerPC (tm) Microprocessor Caches. [Citation Graph (0, 0)][DBLP ] Conf ] B. Provost , E. Sanchez-Sinencio , A. M. Brosa A Unified Approach for a Time-Domain Built-In Self-Test Technique and Fault Detection. [Citation Graph (0, 0)][DBLP ] Conf ] F. S. Bietti , Fabrizio Ferrandi , Franco Fummi , Donatella Sciuto VHDL Testability Analysis Based on Fault Clustering and Implicit Fault Injection. [Citation Graph (0, 0)][DBLP ] Conf ] Hendrawan Soeleman , Dinesh Somasekhar , Kaushik Roy IDD Waveforms Analysis for Testing of Domino and Low Voltage Static CMOS Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Kaamran Raahemifar , Majid Ahmadi A Design-for-Testability Technique for Detecting Delay Faults in Logic Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Robert H. Caverly Development of a CMOS Cell Library for RF Wireless and Telecommunications Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Carlo Samori , Andrea L. Lacaita , Alfio Zanchi , P. Vita Design Issues of LC Tuned Oscillators for Integrated Transceivers. [Citation Graph (0, 0)][DBLP ] Conf ] Massimo Alioto , Gaetano Palumbo Novel Simple Models Of Cml Propagation Delay. [Citation Graph (0, 0)][DBLP ] Conf ] John R. Long Next-Generation Narrowband RF Front-Ends in Silicon IC Technology. [Citation Graph (0, 0)][DBLP ] Conf ] Hassan O. Elwan , Mohammed Ismail Low Voltage Low power CMOS AGC circuit for wireless communication. [Citation Graph (0, 0)][DBLP ] Conf ] Louis Luh , John Choma Jr. , Jeffrey T. Draper A Continuous-Time Switched-Current Sigma-Delta Modulator with Reduced Loop Delay. [Citation Graph (0, 0)][DBLP ] Conf ] Wilsin Gosti , Alberto L. Sangiovanni-Vincentelli , Tiziano Villa , Alexander Saldanha An Exact Input Encoding Algorithm for BDDs Representing FSMs. [Citation Graph (0, 0)][DBLP ] Conf ] Sudhakar Bobba , Ibrahim N. Hajj Maximum Current Estimation in Programmable Logic Arrays. [Citation Graph (0, 0)][DBLP ] Conf ] Vishwani D. Agrawal , Sharad C. Seth Mutually Disjoint Signals and Probability Calculation in Digital Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Travis E. Doom , Jennifer L. White , Anthony S. Wojcik , Gregory H. Chisholm Identifying High-Level Components in Combinational Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Anthony D. Johnson Local Optimality Theory in VLSI Channel Routing: Composite Cyclic Vertical Constraints. [Citation Graph (0, 0)][DBLP ] Conf ] Wolfgang Günther , Rolf Drechsler Linear Transformations and Exact Minimization of BDDs. [Citation Graph (0, 0)][DBLP ] Conf ] Luca Benini , Giovanni De Micheli , Antonio Lioy , Enrico Macii , Giuseppe Odasso , Massimo Poncino Timed Supersetting and the Synthesis of Telescopic Units. [Citation Graph (0, 0)][DBLP ] Conf ] Sadiq M. Sait , Habib Youssef , Munir M. Zahra Tabu Search Based Circuit Optimization. [Citation Graph (0, 0)][DBLP ] Conf ] Dirk Stroobandt , Fadi J. Kurdahi On the Characterization of Multi-Point Nets in Electronic Designs. [Citation Graph (0, 0)][DBLP ] Conf ] Mostafa M. Aref , Khaled M. Elleithy HOOVER: Hardware Object-Oriented Verification. [Citation Graph (0, 0)][DBLP ] Conf ] Otmane Aït Mohamed , Eduard Cerny , Xiaoyu Song MDG-based Verification by Retiming and Combinational Transformations. [Citation Graph (0, 0)][DBLP ] Conf ] Arun Chandra , Li-C. Wang , Magdy S. Abadir Practical Considerations in Formal Equivalence Checking of PowerPC(tm) Microprocessors. [Citation Graph (0, 0)][DBLP ] Conf ] Jianping Lu , Sofiène Tahar Practical Approaches to the Automatic Verification of an ATM Switch Fabric Using VIS. [Citation Graph (0, 0)][DBLP ] Conf ] Mark A. Franklin , Prithvi Prabhu Performance Optimization of Self-Timed Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Ahmad S. Al-Mulhem , Alaaeldin Amin , Habib Youssef Stochastic Evolution Algorithm For Technology Mapping. [Citation Graph (0, 0)][DBLP ] Conf ] Kaisheng Wang , Ted Zhihong Yu , Edwin Hsing-Mean Sha RCRS: A Framework for Loop Scheduling with Limited Number of Registers. [Citation Graph (0, 0)][DBLP ] Conf ] Herwig Van Marck , Jo Depreitere , Dirk Stroobandt , Jan Van Campenhout A Quantitative Study of the Benefits of Area-I/O in FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Dale E. Hocevar , Ching-Yu Hung , Dan Pickens , Sundararajan Sriram Top-Down Design Using Cycle Based Simulation: an MPEG A/V Decoder Example. [Citation Graph (0, 0)][DBLP ] Conf ] Jim E. Crenshaw , Majid Sarrafzadeh Low Power Driven Scheduling and Binding. [Citation Graph (0, 0)][DBLP ] Conf ] Muhammad M. Khellah , Mohamed I. Elmasry Effective Capacitance Macro-Modelling for Architectural-Level Power Estimation. [Citation Graph (0, 0)][DBLP ] Conf ] Vamsi Krishna , N. Ranganathan A Methodology for High Level Power Estimation and Exploration. [Citation Graph (0, 0)][DBLP ] Conf ] S. Gailhard , Nathalie Julien , Jean-Philippe Diguet , Eric Martin How to Transform an Architectural Synthesis Tool for Low Power VLSI Designs. [Citation Graph (0, 0)][DBLP ] Conf ] Karen C. Davis , Satish Venkatesan , Lois M. L. Delcambre Sharing Electronic Design Data Via Semantic Spaces. [Citation Graph (0, 0)][DBLP ] Conf ] Rick Miller VHDL-based EDA Tool Implementation with Java. [Citation Graph (0, 0)][DBLP ] Conf ] David Hertweck , Mihaela Nica , Sang-Eon Park , Carla N. Purdy Standard Data Representations for VLSI Algorithm Development. [Citation Graph (0, 0)][DBLP ] Conf ] Teruhisa Hochin , Tatsuo Tsuji A Storage Structure for Graph-Oriented Databases Using an Array of Element Types. [Citation Graph (0, 0)][DBLP ] Conf ] 