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S. K. Nandy :
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Raghu Anantharangachar , Gorur N. Shrinivas , S. K. Nandy Towards Self-Composing, Prioritized and Consequential Services. [Citation Graph (0, 0)][DBLP ] IEEE SCC, 2006, pp:518- [Conf ] H. Pradeep Rao , S. K. Nandy , M. N. V. Satya Kiran Simultaneous MultiStreaming for Complexity-Effective VLIW Architectures. [Citation Graph (0, 0)][DBLP ] Asia-Pacific Computer Systems Architecture Conference, 2003, pp:166-179 [Conf ] K. Kalapriya , S. K. Nandy Throughput Driven, Highly Available Streaming Stored Playback Video Service over a Peer-to-Peer Network. [Citation Graph (0, 0)][DBLP ] AINA, 2005, pp:229-234 [Conf ] K. Kalapriya , S. K. Nandy , K. Venkatesh Babu Can Streaming Of Stored Playback Video Be Supported On Peer to Peer Infrastructure? [Citation Graph (0, 0)][DBLP ] AINA (2), 2004, pp:200-203 [Conf ] K. Kalapriya , S. K. Nandy , Nanjangud C. Narendra A Framework for Measurement of End-To-End Qos Requirements in Loosely Coupled Systems. [Citation Graph (0, 0)][DBLP ] AINA (2), 2006, pp:926- [Conf ] Mythri Alle , Jayanta Biswas , S. K. Nandy High Performance VLSI Architecture Design for H.264 CAVLC Decoder. [Citation Graph (0, 0)][DBLP ] ASAP, 2006, pp:317-322 [Conf ] Sandeep B. Singh , Jayanta Biswas , S. K. Nandy A Cost Effective Pipelined Divider for Double Precision Floating Point Number. [Citation Graph (0, 0)][DBLP ] ASAP, 2006, pp:132-137 [Conf ] Subhasis Banerjee , G. Surendra , S. K. Nandy Exploiting program execution phases to trade power and performance for media workload. [Citation Graph (0, 0)][DBLP ] ASP-DAC, 2004, pp:387-389 [Conf ] G. Surendra , Subhasis Banerjee , S. K. Nandy Power-performance trade-off using pipeline delays. [Citation Graph (0, 0)][DBLP ] ASP-DAC, 2004, pp:384-386 [Conf ] K. Kalapriya , S. K. Nandy , Deepti Srinivasan , R. Uma Maheshwari , V. Satish A framework for resource discovery in pervasive computing for mobile aware task execution. [Citation Graph (0, 0)][DBLP ] Conf. Computing Frontiers, 2004, pp:70-77 [Conf ] Narasimha B. Bhat , S. K. Nandy Special Purpose Architecture for Accelerating Bitmap DRC. [Citation Graph (0, 0)][DBLP ] DAC, 1989, pp:674-677 [Conf ] Debabrata Ghosh , S. K. Nandy , P. Sadayappan , K. Parthasarathy Architectural Synthesis of Performance-Driven Multipliers with Accumulator Interleaving. [Citation Graph (0, 0)][DBLP ] DAC, 1993, pp:303-307 [Conf ] Satya Kiran , M. N. Jayram , Pradeep Rao , S. K. Nandy A complexity effective communication model for behavioral modeling of signal processing applications. [Citation Graph (0, 0)][DBLP ] DAC, 2003, pp:412-415 [Conf ] S. K. Nandy , L. V. Ramakrishnan Dual quadtree representation for VLSI designs. [Citation Graph (0, 0)][DBLP ] DAC, 1986, pp:663-666 [Conf ] M. Srikanth Rao , S. K. Nandy Power minimization using control generated clocks. [Citation Graph (0, 0)][DBLP ] DAC, 2000, pp:794-799 [Conf ] G. Surendra , Subhasis Banerjee , S. K. Nandy Enhancing Speedup in Network Processing Applications by Exploiting Instruction Reuse with Flow Aggregation. [Citation Graph (0, 0)][DBLP ] DATE, 2003, pp:10784-10789 [Conf ] K. C. Nainwal , J. Lakshmi , S. K. Nandy , Ranjani Narayan , Keshavan Varadarajan A Framework for QoS Adaptive Grid Meta Scheduling. [Citation Graph (0, 0)][DBLP ] DEXA Workshops, 2005, pp:292-296 [Conf ] H. Sarojadevi , S. K. Nandy , S. Balakrishnan Enforcing Cache Coherence at Data Sharing Boundaries without Global Control: A Hardware-Software Approach (Research Note). [Citation Graph (0, 0)][DBLP ] Euro-Par, 2002, pp:543-546 [Conf ] K. Kalapriya , S. K. Nandy , V. Satish , R. Uma Maheshwari , Deepti Srinivas An Architectural View of the Entities Required for Execution of Task in Pervasive Space. [Citation Graph (0, 0)][DBLP ] FTDCS, 2004, pp:37-43 [Conf ] Abhijit M. Lele , S. K. Nandy Harmony - A Framework for Providing Quality of Service in Wireless Mobile Computing Environment. [Citation Graph (0, 0)][DBLP ] HiPC, 1999, pp:299-308 [Conf ] K. Kalapriya , B. R. Raghucharan , Abhijit M. Lele , S. K. Nandy Traffic Profiling for Efficient Network Resource Utilization. [Citation Graph (0, 0)][DBLP ] International Conference on Internet Computing, 2003, pp:789-795 [Conf ] Manvi Agarwal , S. K. Nandy , Jos T. J. van Eijndhoven , S. Balakrishnan Speculative Trace Scheduling in VLIW Processors. [Citation Graph (0, 0)][DBLP ] ICCD, 2002, pp:408-413 [Conf ] Avinash K. Gautam , V. Visvanathan , S. K. Nandy Automatic Generation of Tree Multipliers Using Placement-Driven Netlists. [Citation Graph (0, 0)][DBLP ] ICCD, 1999, pp:285-288 [Conf ] Debabrata Ghosh , S. K. Nandy A 400 MHz Wave-Pipelined 8 X 8-Bit Multiplier in CMOS Technology. [Citation Graph (0, 0)][DBLP ] ICCD, 1993, pp:198-201 [Conf ] Abhijit M. Lele , S. K. Nandy , Dick H. J. Epema Design Space Exploration for Orividing QoS Within the Harmony Framework. [Citation Graph (0, 0)][DBLP ] IEEE International Conference on Multimedia and Expo (I), 2000, pp:521-524 [Conf ] K. Kalapriya , S. K. Nandy On the Implementation of a Streaming Video over Peer to Peer network using Middleware Components. [Citation Graph (0, 0)][DBLP ] ICN/ICONS/MCL, 2006, pp:59- [Conf ] S. K. Nandy , Ranjani Narayan , V. Visvanathan , P. Sadayappan , Prashant S. Chauhan A Parallel Progressive Refinement Image Rendering Algorithm on a Scalable Multithreaded VLSI Processor Array. [Citation Graph (0, 0)][DBLP ] ICPP, 1993, pp:94-97 [Conf ] A. Ahmed , S. K. Nandy , Paul Sathya Content adaptive motion estimation for mobile video encoders. [Citation Graph (0, 0)][DBLP ] ISCAS (2), 2001, pp:237-240 [Conf ] Amitabh Menon , S. K. Nandy , Mahesh Mehendale Multivoltage scheduling with voltage-partitioned variable storage. [Citation Graph (0, 0)][DBLP ] ISLPED, 2003, pp:298-301 [Conf ] J. Lakshmi , S. K. Nandy , Ranjani Narayan , Keshavan Varadarajan Framework for Enabling Highly Available Distributed Applications for Utility Computing. [Citation Graph (0, 0)][DBLP ] ISPA, 2006, pp:549-560 [Conf ] Keshavan Varadarajan , S. K. Nandy , Vishal Sharda , Amrutur Bharadwaj , Ravi R. Iyer , Srihari Makineni , Donald Newell Molecular Caches: A caching structure for dynamic creation of application-specific Heterogeneous cache regions. [Citation Graph (0, 0)][DBLP ] MICRO, 2006, pp:433-442 [Conf ] Manvi Agarwal , S. K. Nandy , Jos T. J. van Eijndhoven , S. Balakrishnan On the Benefits of Speculative Trace Scheduling in VLIW Processors. [Citation Graph (0, 0)][DBLP ] PDPTA, 2002, pp:822-828 [Conf ] Debabrata Ghosh , S. K. Nandy , K. Parthasarathy TWTXBB: A Low Latency, High Throughput Multiplier Architecture Using a New 4 --> 2 Compressor. [Citation Graph (0, 0)][DBLP ] VLSI Design, 1994, pp:77-82 [Conf ] Debabrata Ghosh , S. K. Nandy , K. Parthasarathy , V. Visvanathan NPCPL: Normal Process Complementary Pass Transistor Logic for Low Latency, High Throughput Designs. [Citation Graph (0, 0)][DBLP ] VLSI Design, 1993, pp:341-346 [Conf ] Debabrata Ghosh , Shamik Sural , S. K. Nandy A 600MHz Half-Bit Level Pipelined Multiplier Macrocell. [Citation Graph (0, 0)][DBLP ] VLSI Design, 1994, pp:95-100 [Conf ] A. Giri , V. Visvanathan , S. K. Nandy , S. K. Ghoshal High Speed Digital Filtering on SRAM-Based FPGAs. [Citation Graph (0, 0)][DBLP ] VLSI Design, 1994, pp:229-232 [Conf ] Abhijit M. Lele , S. K. Nandy Architecture of Reconfigurable a Low Power Gigabit AT Switch. [Citation Graph (0, 0)][DBLP ] VLSI Design, 2001, pp:242-247 [Conf ] S. Ramanathan , V. Visvanathan , S. K. Nandy Synthesis of Configurable Architectures for DSP Algorithms. [Citation Graph (0, 0)][DBLP ] VLSI Design, 1999, pp:350-357 [Conf ] G. N. Rathna , S. K. Nandy , K. Parthasarathy A Methodology for Architecture Synthesis of Cascaded IIR Filters on TLU FPGAs. [Citation Graph (0, 0)][DBLP ] VLSI Design, 1994, pp:225-228 [Conf ] G. Surendra , S. K. Nandy , Paul Sathya ReDeEm_RTL: A Software Tool for Customizing Soft Cells for Embedded Applications. [Citation Graph (0, 0)][DBLP ] VLSI Design, 2001, pp:85-90 [Conf ] G. Surendra , Subhasis Banerjee , S. K. Nandy On the effectiveness of prefetching and reuse in reducing L1 data cache traffic: a case study of Snort. [Citation Graph (0, 0)][DBLP ] WMPI, 2004, pp:88-95 [Conf ] H. Sarojadevi , S. K. Nandy , S. Balakrishnan On the Correctness of Program Execution When Cache Coherence Is Maintained Locally at Data-Sharing Boundaries in Distributed Shared Memory Multiprocessors. [Citation Graph (0, 0)][DBLP ] International Journal of Parallel Programming, 2004, v:32, n:5, pp:415-446 [Journal ] G. Surendra , Subhasis Banerjee , S. K. Nandy On the Effectiveness of Flow Aggregation in Improving Instruction Reuse in Network Processing Applications. [Citation Graph (0, 0)][DBLP ] International Journal of Parallel Programming, 2003, v:31, n:6, pp:469-487 [Journal ] Vinod Menezes , S. K. Nandy , Biswadip Mitra Signal compression through spatial frequency-based motion estimation. [Citation Graph (0, 0)][DBLP ] Integration, 1997, v:22, n:1-2, pp:115-135 [Journal ] S. Ramanathan , V. Visvanathan , S. K. Nandy Synthesis of ASIPs for DSP algorithms. [Citation Graph (0, 0)][DBLP ] Integration, 1999, v:28, n:1, pp:13-32 [Journal ] Abhijit M. Lele , S. K. Nandy , Dick H. J. Epema Harmony - An Architecture for Providing Quality of Service in Mobile Computing Environments. [Citation Graph (0, 0)][DBLP ] Journal of Interconnection Networks, 2000, v:1, n:3, pp:247-266 [Journal ] Debabrata Ghosh , S. K. Nandy Design and realization of high-performance wave-pipelined 8×8 b multiplier in CMOS technology. [Citation Graph (0, 0)][DBLP ] IEEE Trans. VLSI Syst., 1995, v:3, n:1, pp:36-48 [Journal ] Arasu T. Senthil , C. P. Ravikumar , S. K. Nandy Low-Power Hierarchical Scan Test for Multiple Clock Domains. [Citation Graph (0, 0)][DBLP ] J. Low Power Electronics, 2007, v:3, n:1, pp:106-118 [Journal ] I/O Virtualization Architecture for Security. [Citation Graph (, )][DBLP ] RECONNECT: A NoC for polymorphic ASICs using a low overhead single cycle router. [Citation Graph (, )][DBLP ] Reconfigurable Viterbi decoder on mesh connected multiprocessor architecture. [Citation Graph (, )][DBLP ] Synthesis of application accelerators on Runtime Reconfigurable Hardware. [Citation Graph (, )][DBLP ] Architecture of a polymorphic ASIC for interoperability across multi-mode H.264 decoders. [Citation Graph (, )][DBLP ] An Input Triggered Polymorphic ASIC for H.264 Decoding. [Citation Graph (, )][DBLP ] Program Phase Directed Dynamic Cache Way Reconfiguration for Power Efficiency. [Citation Graph (, )][DBLP ] Streaming FFT on REDEFINE-v2: an application-architecture design space exploration. [Citation Graph (, )][DBLP ] REDEFINE: Architecture of a SoC Fabric for Runtime Composition of Computation Structures. [Citation Graph (, )][DBLP ] I/O Device Virtualization in the Multi-core era, a QoS Perspective. [Citation Graph (, )][DBLP ] Architecture of Run-Time Reconfigurable Channel Decoder. [Citation Graph (, )][DBLP ] Functional and architectural adaptation in pervasive computing environments. [Citation Graph (, )][DBLP ] RETHROTTLE: Execution throttling in the REDEFINE SoC architecture. [Citation Graph (, )][DBLP ] High-throughput flexible constraint length Viterbi decoders on de Bruijn, shuffle-exchange and butterfly connected architectures. [Citation Graph (, )][DBLP ] Compiling Techniques for Coarse Grained Runtime Reconfigurable Architectures. [Citation Graph (, )][DBLP ] Search in 0.007secs, Finished in 0.012secs