Conferences in DBLP

International Symposium om Computer Architecture (ISCA) (isca)
2002 (conf/isca/2002)

1. Allan Hartstein, Thomas R. Puzak
   The Optimum Pipeline Depth for a Microprocessor. [Citation Graph (0, 0)][DBLP]
   ISCA, 2002, pp:7-13 [Conf]
   
2. M. S. Hrishikesh, Doug Burger, Stephen W. Keckler, Premkishore Shivakumar, Norman P. Jouppi, Keith I. Farkas
   The Optimal Logic Depth Per Pipeline Stage is 6 to 8 FO4 Inverter Delays. [Citation Graph (0, 0)][DBLP]
   ISCA, 2002, pp:14-24 [Conf]
   
3. Eric Sprangle, Doug Carmean
   Increasing Processor Performance by Implementing Deeper Pipelines. [Citation Graph (0, 0)][DBLP]
   ISCA, 2002, pp:25-0 [Conf]
   
4. Dan Ernst, Todd M. Austin
   Efficient Dynamic Scheduling Through Tag Elimination. [Citation Graph (0, 0)][DBLP]
   ISCA, 2002, pp:37-46 [Conf]
   
5. Brian A. Fields, Rastislav Bodík, Mark D. Hill
   Slack: Maximizing Performance Under Technological Constraints. [Citation Graph (0, 0)][DBLP]
   ISCA, 2002, pp:47-58 [Conf]
   
6. Alvin R. Lebeck, Tong Li, Eric Rotenberg, Jinson Koppanalil, Jaidev P. Patwardhan
   A Large, Fast Instruction Window for Tolerating Cache Misses. [Citation Graph (0, 0)][DBLP]
   ISCA, 2002, pp:59-70 [Conf]
   
7. Ho-Seop Kim, James E. Smith
   An Instruction Set and Microarchitecture for Instruction Level Distributed Processing. [Citation Graph (0, 0)][DBLP]
   ISCA, 2002, pp:71-0 [Conf]
   
8. T. N. Vijaykumar, Irith Pomeranz, Karl Cheng
   Transient-Fault Recovery Using Simultaneous Multithreading. [Citation Graph (0, 0)][DBLP]
   ISCA, 2002, pp:87-98 [Conf]
   
9. Shubhendu S. Mukherjee, Michael Kontz, Steven K. Reinhardt
   Detailed Design and Evaluation of Redundant Multithreading Alternatives. [Citation Graph (0, 0)][DBLP]
   ISCA, 2002, pp:99-110 [Conf]
   
10. Milos Prvulovic, Josep Torrellas, Zheng Zhang
    ReVive: Cost-Effective Architectural Support for Rollback Recovery in Shared-Memory Multiprocessors. [Citation Graph (0, 0)][DBLP]
    ISCA, 2002, pp:111-122 [Conf]
    
11. Daniel J. Sorin, Milo M. K. Martin, Mark D. Hill, David A. Wood
    SafetyNet: Improving the Availability of Shared Memory Multiprocessors with Global Checkpoint/Recovery. [Citation Graph (0, 0)][DBLP]
    ISCA, 2002, pp:123-0 [Conf]
    
12. Seongmoo Heo, Kenneth Barr, Mark Hampton, Krste Asanovic
    Dynamic Fine-Grain Leakage Reduction Using Leakage-Biased Bitlines. [Citation Graph (0, 0)][DBLP]
    ISCA, 2002, pp:137-147 [Conf]
    
13. Krisztián Flautner, Nam Sung Kim, Steve Martin, David Blaauw, Trevor N. Mudge
    Drowsy Caches: Simple Techniques for Reducing Leakage Power. [Citation Graph (0, 0)][DBLP]
    ISCA, 2002, pp:148-157 [Conf]
    
14. Anoop Iyer, Diana Marculescu
    Power and Performance Evaluation of Globally Asynchronous Locally Synchronous Processors. [Citation Graph (0, 0)][DBLP]
    ISCA, 2002, pp:158-0 [Conf]
    
15. Yan Solihin, Josep Torrellas, Jaejin Lee
    Using a User-Level Memory Thread for Correlation Prefetching. [Citation Graph (0, 0)][DBLP]
    ISCA, 2002, pp:171-182 [Conf]
    
16. Jarrod A. Lewis, Mikko H. Lipasti, Bryan Black
    Avoiding Initialization Misses to the Heap. [Citation Graph (0, 0)][DBLP]
    ISCA, 2002, pp:183-194 [Conf]
    
17. Gokul B. Kandiraju, Anand Sivasubramaniam
    Going the Distance for TLB Prefetching: An Application-Driven Study. [Citation Graph (0, 0)][DBLP]
    ISCA, 2002, pp:195-0 [Conf]
    
18. Zhigang Hu, Margaret Martonosi, Stefanos Kaxiras
    Timekeeping in the Memory System: Predicting and Optimizing Memory Behavior. [Citation Graph (0, 0)][DBLP]
    ISCA, 2002, pp:209-220 [Conf]
    
19. Ilhyun Kim, Mikko H. Lipasti
    Implementing Optimizations at Decode Time. [Citation Graph (0, 0)][DBLP]
    ISCA, 2002, pp:221-232 [Conf]
    
20. Ashutosh S. Dhodapkar, James E. Smith
    Managing Multi-Configuration Hardware via Dynamic Working Set Analysis. [Citation Graph (0, 0)][DBLP]
    ISCA, 2002, pp:233-0 [Conf]
    
21. Philip Buonadonna, David E. Culler
    Queue Pair IP: A Hybrid Architecture for System Area Networks. [Citation Graph (0, 0)][DBLP]
    ISCA, 2002, pp:247-256 [Conf]
    
22. Yuanyuan Zhou, Kai Li, Angelos Bilas, Suresh Jagannathan, Cezary Dubnicki, James Philbin
    Experiences with VI Communication for Database Storage. [Citation Graph (0, 0)][DBLP]
    ISCA, 2002, pp:257-0 [Conf]
    
23. Alex Pajuelo, Antonio González, Mateo Valero
    Speculative Dynamic Vectorization. [Citation Graph (0, 0)][DBLP]
    ISCA, 2002, pp:271-280 [Conf]
    
24. Roger Espasa, Federico Ardanaz, Julio Gago, Roger Gramunt, Isaac Hernandez, Toni Juan, Joel S. Emer, Stephen Felix, P. Geoffrey Lowney, Matthew Mattina, André Seznec
    Tarantula: A Vector Extension to the Alpha Architecture. [Citation Graph (0, 0)][DBLP]
    ISCA, 2002, pp:281-0 [Conf]
    
25. André Seznec, Stephen Felix, Venkata Krishnan, Yiannakis Sazeides
    Design Tradeoffs for the Alpha EV8 Conditional Branch Predictor. [Citation Graph (0, 0)][DBLP]
    ISCA, 2002, pp:295-306 [Conf]
    
26. Robert S. Chappell, Francis Tseng, Yale N. Patt, Adi Yoaz
    Difficult-Path Branch Prediction Using Subordinate Microthreads. [Citation Graph (0, 0)][DBLP]
    ISCA, 2002, pp:307-317 [Conf]
    
27. Steven E. Raasch, Nathan L. Binkert, Steven K. Reinhardt
    A Scalable Instruction Queue Design Using Dependence Chains. [Citation Graph (0, 0)][DBLP]
    ISCA, 2002, pp:318-0 [Conf]