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Krzysztof Kuchcinski :
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Krzysztof Kuchcinski , Wlodzimierz Drabent , Jan Maluszynski Automatic Diagnosis of VLSI Digital Circuits Using Algorithmic Debugging. [Citation Graph (0, 0)][DBLP ] AADEBUG, 1993, pp:350-367 [Conf ] Krzysztof Kuchcinski , Bogdan Wiszniewski Path analysis of distributed programs. [Citation Graph (0, 0)][DBLP ] ACM Conference on Computer Science, 1988, pp:320-328 [Conf ] Flavius Gruian , Krzysztof Kuchcinski LEneS: task scheduling for low-energy systems using variable supply voltage processors. [Citation Graph (0, 0)][DBLP ] ASP-DAC, 2001, pp:449-455 [Conf ] Radoslaw Szymanek , Krzysztof Kuchcinski A constructive algorithm for memory-aware task assignment and scheduling. [Citation Graph (0, 0)][DBLP ] CODES, 2001, pp:147-152 [Conf ] Radoslaw Szymanek , Krzysztof Kuchcinski Partial task assignment of task graphs under heterogeneous resource constraints. [Citation Graph (0, 0)][DBLP ] DAC, 2003, pp:244-249 [Conf ] Petru Eles , Krzysztof Kuchcinski , Zebo Peng , Alexa Doboli , Paul Pop Scheduling of Conditional Process Graphs for the Synthesis of Embedded Systems. [Citation Graph (0, 0)][DBLP ] DATE, 1998, pp:132-0 [Conf ] Krzysztof Kuchcinski Integrated Resource Assignment and Scheduling of Task Graphs Using Finite Domain Constraints. [Citation Graph (0, 0)][DBLP ] DATE, 1999, pp:772-773 [Conf ] Radoslaw Szymanek , Francky Catthoor , Krzysztof Kuchcinski Time-Energy Design Space Exploration for Multi-Layer Memory Architectures. [Citation Graph (0, 0)][DBLP ] DATE, 2004, pp:318-323 [Conf ] Ali R. Iranpour , Krzysztof Kuchcinski Evaluation of SIMD Architecture Enhancement in Embedded Processors for MPEG-4. [Citation Graph (0, 0)][DBLP ] DSD, 2004, pp:262-269 [Conf ] Per Andersson , Krzysztof Kuchcinski Java to Hardware Compilation for non Data Flow Applications. [Citation Graph (0, 0)][DBLP ] DSD, 2005, pp:330-337 [Conf ] Per Andersson , Krzysztof Kuchcinski , Klas Nordberg , Patrick Doherty Integrating a Computational Model and a Run Time System for Image Processing on a UAV. [Citation Graph (0, 0)][DBLP ] DSD, 2002, pp:102-109 [Conf ] Krzysztof Kuchcinski , Christophe Wolinski Synthesis of Conditional Behaviors Using Hierarchical Conditional Dependency Graphs and Constraint Logic Programming. [Citation Graph (0, 0)][DBLP ] DSD, 2001, pp:220-227 [Conf ] Christophe Wolinski , Krzysztof Kuchcinski A Constraints Programming Approach for Fabric Cell Synthesis. [Citation Graph (0, 0)][DBLP ] DSD, 2005, pp:356-363 [Conf ] Christophe Wolinski , Krzysztof Kuchcinski , Maya Gokhale A Constraints Programming Approach to Communication Scheduling on SoPC Architectures. [Citation Graph (0, 0)][DBLP ] DSD, 2004, pp:308-315 [Conf ] Ali R. Iranpour , Krzysztof Kuchcinski Performance Improvement for H.264 Video Encoding using ILP Embedded Processor. [Citation Graph (0, 0)][DBLP ] DSD, 2006, pp:515-521 [Conf ] Patrik Dohrty , Gösta H. Granlund , Krzysztof Kuchcinski , Erik Sandewall , Klas Nordberg , Erik Skarman , Johan Wiklund The WITAS Unmanned Aerial Vehicle Project. [Citation Graph (0, 0)][DBLP ] ECAI, 2000, pp:747-755 [Conf ] Per Andersson , Krzysztof Kuchcinski Distinguished Paper: Automatic Local Memory Architecture Generation for Data Reuse in Custom Data Paths. [Citation Graph (0, 0)][DBLP ] ERSA, 2004, pp:137-144 [Conf ] Radoslaw Szymanek , Francky Catthoor , Krzysztof Kuchcinski Data assignment and access scheduling exploration for multi-layer memory architectures. [Citation Graph (0, 0)][DBLP ] ESTImedia, 2004, pp:61-66 [Conf ] Per Andersson , Krzysztof Kuchcinski Performance Oriented Partitioning for Time-Multiplexed FPGA's. [Citation Graph (0, 0)][DBLP ] EUROMICRO, 2000, pp:1060-1066 [Conf ] Petru Eles , Krzysztof Kuchcinski , Zebo Peng , Alexa Doboli , Paul Pop Process Scheduling for Performance Estimation and Synthesis of Hardware/Software Systems. [Citation Graph (0, 0)][DBLP ] EUROMICRO, 1998, pp:10168-0 [Conf ] Flavius Gruian , Krzysztof Kuchcinski Operation Binding and Scheduling for Low Power Using Constraint Logic Programming. [Citation Graph (0, 0)][DBLP ] EUROMICRO, 1998, pp:10083-10090 [Conf ] Flavius Gruian , Krzysztof Kuchcinski Low-Energy Directed Architecture Selection and Task Scheduling for System-Level Design. [Citation Graph (0, 0)][DBLP ] EUROMICRO, 1999, pp:1296-1302 [Conf ] Peter Grün , Petru Eles , Krzysztof Kuchcinski , Zebo Peng Automatic Parallelization of a Petri Net-Based Design Representation for High-Level Synthesis. [Citation Graph (0, 0)][DBLP ] EUROMICRO, 1996, pp:185-192 [Conf ] Krzysztof Kuchcinski An Approach to High-Level Synthesis Using Constraint Logic Programming. [Citation Graph (0, 0)][DBLP ] EUROMICRO, 1998, pp:10074-10082 [Conf ] Krzysztof Kuchcinski Synthesis of Distributed Embedded Systems. [Citation Graph (0, 0)][DBLP ] EUROMICRO, 1999, pp:1022-1028 [Conf ] Radoslaw Szymanek , Krzysztof Kuchcinski Task Assignment and Scheduling under Memory Constraints. [Citation Graph (0, 0)][DBLP ] EUROMICRO, 2000, pp:1084-1090 [Conf ] Radoslaw Szymanek , Krzysztof Kuchcinski Design Space Exploration in System Level Synthesis under Memory Constraints. [Citation Graph (0, 0)][DBLP ] EUROMICRO, 1999, pp:1029-0 [Conf ] Christophe Wolinski , Krzysztof Kuchcinski , Maya Gokhale A constraints programming approach to communication scheduling on SoPC architectures. [Citation Graph (0, 0)][DBLP ] FPGA, 2004, pp:252- [Conf ] Henrik Svensson , Viktor Öwall , Krzysztof Kuchcinski Implementation aspects of a novel speech packet loss concealment method. [Citation Graph (0, 0)][DBLP ] ISCAS (3), 2005, pp:2867-2870 [Conf ] Flavius Gruian , Krzysztof Kuchcinski Uncertainty-based scheduling: energy-efficient ordering for tasks with variable execution time. [Citation Graph (0, 0)][DBLP ] ISLPED, 2003, pp:465-468 [Conf ] Petru Eles , Zebo Peng , Krzysztof Kuchcinski , Alex Doboli Hardware/Software Partitioning with Iterative Improvement Heuristics. [Citation Graph (0, 0)][DBLP ] ISSS, 1996, pp:71-76 [Conf ] Krzysztof Kuchcinski Embedded System Synthesis by Timing Constraints Solving. [Citation Graph (0, 0)][DBLP ] ISSS, 1997, pp:50-57 [Conf ] Xinli Gu , Krzysztof Kuchcinski , Zebo Peng An Efficient and Economic Partitioning Approach for Testability. [Citation Graph (0, 0)][DBLP ] ITC, 1995, pp:403-412 [Conf ] Flavius Gruian , Per Andersson , Krzysztof Kuchcinski , Martin Schoeberl Automatic generation of application-specific systems based on a micro-programmed Java core. [Citation Graph (0, 0)][DBLP ] SAC, 2005, pp:879-884 [Conf ] Mats Petter Pettersson , Radoslaw Szymanek , Krzysztof Kuchcinski A CP-LP approach to network management in OSPF routing. [Citation Graph (0, 0)][DBLP ] SAC, 2007, pp:311-315 [Conf ] Ali R. Iranpour , Krzysztof Kuchcinski Memory Architecture Evaluation for Video Encoding on Enhanced Embedded Processors. [Citation Graph (0, 0)][DBLP ] SAMOS, 2006, pp:309-320 [Conf ] Petru Eles , Krzysztof Kuchcinski , Zebo Peng Synthesis of systems specified as interacting VHDL processes. [Citation Graph (0, 0)][DBLP ] Integration, 1996, v:21, n:1-2, pp:113-138 [Journal ] Krzysztof Kuchcinski , Christophe Wolinski Global approach to assignment and scheduling of complex behaviors based on HCDG and constraint programming. [Citation Graph (0, 0)][DBLP ] Journal of Systems Architecture, 2003, v:49, n:12-15, pp:489-503 [Journal ] Zebo Peng , Krzysztof Kuchcinski Automated transformation of algorithms into register-transfer level implementations. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:2, pp:150-166 [Journal ] Krzysztof Kuchcinski Constraints-driven scheduling and resource assignment. [Citation Graph (0, 0)][DBLP ] ACM Trans. Design Autom. Electr. Syst., 2003, v:8, n:3, pp:355-383 [Journal ] Mats Petter Pettersson , Krzysztof Kuchcinski A New Necessary Condition for Shortest Path Routing. [Citation Graph (0, 0)][DBLP ] NET-COOP, 2007, pp:195-204 [Conf ] Identification of Application Specific Instructions Based on Sub-Graph Isomorphism Constraints. [Citation Graph (, )][DBLP ] Constraint-Driven Instructions Selection and Application Scheduling in the DURASE system. [Citation Graph (, )][DBLP ] Load-balancing methods for parallel and distributed constraint solving. [Citation Graph (, )][DBLP ] Automatic Selection of Application-Specific Reconfigurable Processor Extensions. [Citation Graph (, )][DBLP ] A controller testability analysis and enhancement technique. [Citation Graph (, )][DBLP ] Graph Matching Constraints for Synthesis with Complex Components. [Citation Graph (, )][DBLP ] Communication Network Reconfiguration Overhead Optimization in Programmable Processor Array Architectures. [Citation Graph (, )][DBLP ] Architecture-Driven Synthesis of Reconfigurable Cells. [Citation Graph (, )][DBLP ] Computation Patterns Identification for Instruction Set Extensions Implemented as Reconfigurable Hardware. [Citation Graph (, )][DBLP ] How Constrains Programming Can Help You in the Generation of Optimized Application Specific Reconfigurable Processor Extensions. [Citation Graph (, )][DBLP ] Design space exploration for optimal memory mapping of data and instructions in multimedia applications to Scratch-Pad Memories. [Citation Graph (, )][DBLP ] Timing constraint specification and synthesis in behavioral VHDL. [Citation Graph (, )][DBLP ] Testability analysis and improvement from VHDL behavioral specifications. [Citation Graph (, )][DBLP ] Synthesis of VHDL concurrent processes. [Citation Graph (, )][DBLP ] Optimization of Routing and Reconfiguration Overhead in Programmable Processor Array Architectures. [Citation Graph (, )][DBLP ] Area and reconfiguration time minimization of the communication network in regular 2D reconfigurable architectures. [Citation Graph (, )][DBLP ] State-copying and Recomputation in Parallel Constraint Programming with Global Constraints. [Citation Graph (, )][DBLP ] Parallel Consistency in Constraint Programming. [Citation Graph (, )][DBLP ] Constraint-Driven Identification of Application Specific Instructions in the DURASE System. [Citation Graph (, )][DBLP ] Search in 0.003secs, Finished in 0.452secs