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Author:
Petru Eles: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Zhiyuan He, Gert Jervan, Zebo Peng, Petru Eles
    Hybrid BIST Test Scheduling Based on Defect Probabilities. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2004, pp:230-235 [Conf]
  2. Gert Jervan, Petru Eles, Zebo Peng, Raimund Ubar, Maksim Jenihhin
    Test Time Minimization for Hybrid BIST of Core-Based Systems. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2003, pp:318-325 [Conf]
  3. Anders Larsson, Erik Larsson, Petru Eles, Zebo Peng
    SOC Test Scheduling with Test Set Sharing and Broadcasting. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2005, pp:162-169 [Conf]
  4. Petru Eles, Zebo Peng, Alexa Doboli
    VHDL system-level specification and partitioning in a hardware/software co-synthesis environment. [Citation Graph (0, 0)][DBLP]
    CODES, 1994, pp:49-55 [Conf]
  5. Paul Pop, Petru Eles, Zebo Peng
    Performance estimation for embedded systems with data and control dependencies. [Citation Graph (0, 0)][DBLP]
    CODES, 2000, pp:62-66 [Conf]
  6. Traian Pop, Petru Eles, Zebo Peng
    Holistic scheduling and analysis of mixed time/event-triggered distributed embedded systems. [Citation Graph (0, 0)][DBLP]
    CODES, 2002, pp:187-192 [Conf]
  7. Traian Pop, Petru Eles, Zebo Peng
    Design optimization of mixed time/event-triggered distributed embedded systems. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2003, pp:83-89 [Conf]
  8. Paul Pop, Petru Eles, Zebo Peng
    Scheduling with optimized communication for time-triggered embedded systems. [Citation Graph (0, 0)][DBLP]
    CODES, 1999, pp:178-182 [Conf]
  9. Paul Pop, Petru Eles, Traian Pop, Zebo Peng
    Minimizing system modification in an incremental design approach. [Citation Graph (0, 0)][DBLP]
    CODES, 2001, pp:183-188 [Conf]
  10. Mauricio Varea, Bashir M. Al-Hashimi, Luis Alejandro Cortés, Petru Eles, Zebo Peng
    Symbolic model checking of Dual Transition Petri Nets. [Citation Graph (0, 0)][DBLP]
    CODES, 2002, pp:43-48 [Conf]
  11. Luis Alejandro Cortés, Petru Eles, Zebo Peng
    Quasi-static assignment of voltages and optional cycles for maximizing rewards in real-time systems with energy c-onstraints. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:889-894 [Conf]
  12. Sorin Manolache, Petru Eles, Zebo Peng
    Fault and energy-aware communication mapping with guaranteed latency for applications implemented on NoC. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:266-269 [Conf]
  13. Paul Pop, Petru Eles, Traian Pop, Zebo Peng
    An Approach to Incremental Design of Distributed Embedded Systems. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:450-455 [Conf]
  14. Alexandru Andrei, Marcus T. Schmitz, Petru Eles, Zebo Peng, Bashir M. Al-Hashimi
    Overhead-Conscious Voltage Selection for Dynamic and Leakage Energy Reduction of Time-Constrained Systems. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:518-525 [Conf]
  15. Alexandru Andrei, Marcus T. Schmitz, Petru Eles, Zebo Peng, Bashir M. Al-Hashimi
    Quasi-Static Voltage Scaling for Energy Minimization with Time Constraints. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:514-519 [Conf]
  16. Luis Alejandro Cortés, Petru Eles, Zebo Peng
    Quasi-Static Scheduling for Real-Time Systems with Hard and Soft Tasks. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:1176-1183 [Conf]
  17. Petru Eles, Krzysztof Kuchcinski, Zebo Peng, Alexa Doboli, Paul Pop
    Scheduling of Conditional Process Graphs for the Synthesis of Embedded Systems. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:132-0 [Conf]
  18. Zhiyuan He, Zebo Peng, Petru Eles
    Power constrained and defect-probability driven SoC test scheduling with test set partitioning. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:291-296 [Conf]
  19. Viacheslav Izosimov, Paul Pop, Petru Eles, Zebo Peng
    Design Optimization of Time-and Cost-Constrained Fault-Tolerant Distributed Embedded Systems. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:864-869 [Conf]
  20. Viacheslav Izosimov, Paul Pop, Petru Eles, Zebo Peng
    Synthesis of fault-tolerant schedules with transparency/performance trade-offs for distributed embedded systems. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:706-711 [Conf]
  21. Daniel Karlsson, Petru Eles, Zebo Peng
    Formal verification of systemc designs using a petri-net based representation. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:1228-1233 [Conf]
  22. Sorin Manolache, Petru Eles, Zebo Peng
    Buffer space optimisation with communication synthesis and traffic shaping for NoCs. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:718-723 [Conf]
  23. Paul Pop, Petru Eles, Zebo Peng
    Bus Access Optimization for Distributed Embedded Systems Based on Schedulability Analysis. [Citation Graph (0, 0)][DBLP]
    DATE, 2000, pp:567-0 [Conf]
  24. Paul Pop, Petru Eles, Zebo Peng
    Schedulability Analysis and Optimization for the Synthesis of Multi-Cluster Distributed Embedded Systems. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10184-10189 [Conf]
  25. Paul Pop, Petru Eles, Zebo Peng, Viacheslav Izosimov, Magnus Hellring, Olof Bridal
    Design Optimization of Multi-Cluster Embedded Systems for Real-Time Application. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:1027-1033 [Conf]
  26. Marcus T. Schmitz, Bashir M. Al-Hashimi, Petru Eles
    Energy-Efficient Mapping and Scheduling for DVS Enabled Distributed Embedded Systems. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:514-521 [Conf]
  27. Marcus T. Schmitz, Bashir M. Al-Hashimi, Petru Eles
    A Co-Design Methodology for Energy-Efficient Multi-Mode Embedded Systems with Consideration of Mode Execution Probabilities. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10960-10965 [Conf]
  28. Dong Wu, Bashir M. Al-Hashimi, Petru Eles
    Scheduling and Mapping of Conditional Task Graphs for the Synthesis of Low Power Embedded Systems. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10090-10095 [Conf]
  29. Anders Larsson, Erik Larsson, Petru Eles, Zebo Peng
    A Heuristic for Concurrent SOC Test Scheduling with Compression and Sharing. [Citation Graph (0, 0)][DBLP]
    DDECS, 2007, pp:61-66 [Conf]
  30. Viacheslav Izosimov, Paul Pop, Petru Eles, Zebo Peng
    Synthesis of Fault-Tolerant Embedded Systems with Checkpointing and Replication. [Citation Graph (0, 0)][DBLP]
    DELTA, 2006, pp:440-447 [Conf]
  31. Luis Alejandro Cortés, Petru Eles, Zebo Peng
    Static Scheduling of Monoprocessor Real-Time Systems composed of Hard and Soft Tasks. [Citation Graph (0, 0)][DBLP]
    DELTA, 2004, pp:115-120 [Conf]
  32. Abdil Rashid Mohamed, Zebo Peng, Petru Eles
    A Wiring-Aware Approach to Minimizing Built-in Self-Test Overhead. [Citation Graph (0, 0)][DBLP]
    DELTA, 2004, pp:413-415 [Conf]
  33. Gert Jervan, Petru Eles, Zebo Peng, Raimund Ubar, Maksim Jenihhin
    Hybrid BIST Time Minimization for Core-Based Systems with STUMPS Architecture. [Citation Graph (0, 0)][DBLP]
    DFT, 2003, pp:225-0 [Conf]
  34. Anders Larsson, Erik Larsson, Petru Eles, Zebo Peng
    Buffer and Controller Minimisation for Time-Constrained Testing of System-On-Chip. [Citation Graph (0, 0)][DBLP]
    DFT, 2003, pp:385-392 [Conf]
  35. Zhiyuan He, Zebo Peng, Petru Eles, Paul M. Rosinger, Bashir M. Al-Hashimi
    Thermal-Aware SoC Test Scheduling with Test Set Partitioning and Interleaving. [Citation Graph (0, 0)][DBLP]
    DFT, 2006, pp:477-485 [Conf]
  36. Zhiyuan He, Gert Jervan, Zebo Peng, Petru Eles
    Power-Constrained Hybrid BIST Test Scheduling in an Abort-on-First-Fail Test Environment. [Citation Graph (0, 0)][DBLP]
    DSD, 2005, pp:83-87 [Conf]
  37. Luis Alejandro Cortés, Petru Eles, Zebo Peng
    Hierarchical Modeling and Verification of Embedded Systems. [Citation Graph (0, 0)][DBLP]
    DSD, 2001, pp:63-71 [Conf]
  38. Daniel Karlsson, Petru Eles, Zebo Peng
    A Formal Verification Methodology for IP-based Designs. [Citation Graph (0, 0)][DBLP]
    DSD, 2004, pp:372-379 [Conf]
  39. Daniel Karlsson, Petru Eles, Zebo Peng
    Validation of Embedded Systems Using Formal Method Aided Simulation. [Citation Graph (0, 0)][DBLP]
    DSD, 2005, pp:196-201 [Conf]
  40. Anders Larsson, Erik Larsson, Petru Eles, Zebo Peng
    Optimization of a Bus-based Test Data Transportation Mechanism in System-on-Chip. [Citation Graph (0, 0)][DBLP]
    DSD, 2005, pp:403-411 [Conf]
  41. Abdil Rashid Mohamed, Zebo Peng, Petru Eles
    A Heuristic for Wiring-Aware Built-In Self-Test Synthesis. [Citation Graph (0, 0)][DBLP]
    DSD, 2004, pp:408-415 [Conf]
  42. Dong Wu, Bashir M. Al-Hashimi, Marcus T. Schmitz, Petru Eles
    Power-Composition Profile Driven Co-Synthesis with Power Management Selection for Dynamic and Leakage Energy Reduction. [Citation Graph (0, 0)][DBLP]
    DSD, 2005, pp:34-41 [Conf]
  43. Viacheslav Izosimov, Paul Pop, Petru Eles, Zebo Peng
    Mapping of Fault-Tolerant Applications with Transparency on Distributed Embedded Systems*. [Citation Graph (0, 0)][DBLP]
    DSD, 2006, pp:313-322 [Conf]
  44. Sorin Manolache, Petru Eles, Zebo Peng
    Memory and Time-Efficient Schedulability Analysis of Task Sets with Stochastic Execution Time. [Citation Graph (0, 0)][DBLP]
    ECRTS, 2001, pp:19-0 [Conf]
  45. Traian Pop, Petru Eles, Zebo Peng
    Schedulability Analysis for Distributed Heterogeneous Time/Event Triggered Real-Time Systems. [Citation Graph (0, 0)][DBLP]
    ECRTS, 2003, pp:257-266 [Conf]
  46. Paul Pop, Petru Eles, Zebo Peng, Viacheslav Izosimov
    Schedulability-Driven Partitioning and Mapping for Multi-Cluster Real-Time Systems. [Citation Graph (0, 0)][DBLP]
    ECRTS, 2004, pp:91-100 [Conf]
  47. Luis Alejandro Cortés, Petru Eles, Zebo Peng
    Formal Coverification of Embedded Systems Using Model Checking. [Citation Graph (0, 0)][DBLP]
    EUROMICRO, 2000, pp:1106-1113 [Conf]
  48. Petru Eles, Krzysztof Kuchcinski, Zebo Peng, Alexa Doboli, Paul Pop
    Process Scheduling for Performance Estimation and Synthesis of Hardware/Software Systems. [Citation Graph (0, 0)][DBLP]
    EUROMICRO, 1998, pp:10168-0 [Conf]
  49. Peter Grün, Petru Eles, Krzysztof Kuchcinski, Zebo Peng
    Automatic Parallelization of a Petri Net-Based Design Representation for High-Level Synthesis. [Citation Graph (0, 0)][DBLP]
    EUROMICRO, 1996, pp:185-192 [Conf]
  50. Paul Pop, Petru Eles, Zebo Peng
    An Improved Scheduling Technique for Time-Triggered Embedded Systems. [Citation Graph (0, 0)][DBLP]
    EUROMICRO, 1999, pp:1303-1310 [Conf]
  51. Alexandru Andrei, Marcus T. Schmitz, Petru Eles, Zebo Peng, Bashir M. Al-Hashimi
    Simultaneous communication and processor voltage scaling for dynamic and leakage energy reduction in time-constrained systems. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2004, pp:362-369 [Conf]
  52. Sorin Manolache, Petru Eles, Zebo Peng
    Schedulability analysis of multiprocessor real-time applications with stochastic task execution times. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2002, pp:699-706 [Conf]
  53. Luis Alejandro Cortés, Petru Eles, Zebo Peng
    Definitions of Equivalence for Transformational Synthesis of Embedded Systems. [Citation Graph (0, 0)][DBLP]
    ICECCS, 2000, pp:134-142 [Conf]
  54. Razvan Jigorea, Sorin Manolache, Petru Eles, Zebo Peng
    Modeling of Real-Time Embedded Systems in an Object-Oriented Design Environment with UML. [Citation Graph (0, 0)][DBLP]
    ISORC, 2000, pp:210-0 [Conf]
  55. Petru Eles, Zebo Peng, Krzysztof Kuchcinski, Alex Doboli
    Hardware/Software Partitioning with Iterative Improvement Heuristics. [Citation Graph (0, 0)][DBLP]
    ISSS, 1996, pp:71-76 [Conf]
  56. Luis Alejandro Cortés, Petru Eles, Zebo Peng
    Verification of Embedded Systems using a Petri Net based Representation. [Citation Graph (0, 0)][DBLP]
    ISSS, 2000, pp:149-156 [Conf]
  57. Petru Eles, Zebo Peng, Daniel Karlsson
    Formal Verification in a Component-Based Reuse Methodology. [Citation Graph (0, 0)][DBLP]
    ISSS, 2002, pp:156-161 [Conf]
  58. Paul Pop, Petru Eles, Zebo Peng
    Schedulability-driven frame packing for multi-cluster distributed embedded systems. [Citation Graph (0, 0)][DBLP]
    LCTES, 2003, pp:113-122 [Conf]
  59. Peter Nilsson, Petru Eles, Hannu Tenhunen
    SOCWARE: A New Swedish Design Cluster for System-on-Chip. [Citation Graph (0, 0)][DBLP]
    MSE, 2001, pp:44-45 [Conf]
  60. Sorin Manolache, Petru Eles, Zebo Peng
    Optimization of Soft Real-Time Systems with Deadline Miss Ratio Constraints. [Citation Graph (0, 0)][DBLP]
    IEEE Real-Time and Embedded Technology and Applications Symposium, 2004, pp:562-570 [Conf]
  61. Luis Alejandro Cortés, Petru Eles, Zebo Peng
    Quasi-Static Scheduling for Multiprocessor Real-Time Systems with Hard and Soft Tasks. [Citation Graph (0, 0)][DBLP]
    RTCSA, 2005, pp:422-428 [Conf]
  62. Luis Alejandro Cortés, Petru Eles, Zebo Peng
    A Quasi-Static Approach to Minimizing Energy Consumption in Real-Time Systems under Reward Constraints. [Citation Graph (0, 0)][DBLP]
    RTCSA, 2006, pp:279-286 [Conf]
  63. Paul Pop, Petru Eles, Zebo Peng
    Schedulability-Driven Communication Synthesis for Time Triggered Embedded Systems. [Citation Graph (0, 0)][DBLP]
    RTCSA, 1999, pp:287-294 [Conf]
  64. Traian Pop, Paul Pop, Petru Eles, Zebo Peng
    Optimization of Hierarchically Scheduled Heterogeneous Embedded Systems. [Citation Graph (0, 0)][DBLP]
    RTCSA, 2005, pp:67-71 [Conf]
  65. Radu Marculescu, Petru Eles
    Guest Editors' Introduction: Designing Real-Time Embedded Multimedia Systems. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2004, v:21, n:5, pp:354-356 [Journal]
  66. Petru Eles, Krzysztof Kuchcinski, Zebo Peng
    Synthesis of systems specified as interacting VHDL processes. [Citation Graph (0, 0)][DBLP]
    Integration, 1996, v:21, n:1-2, pp:113-138 [Journal]
  67. Abdil Rashid Mohamed, Zebo Peng, Petru Eles
    A Wiring-Aware Approach to Minimizing Built-In Self-Test Overhead. [Citation Graph (0, 0)][DBLP]
    J. Comput. Sci. Technol., 2005, v:20, n:2, pp:216-223 [Journal]
  68. Gert Jervan, Petru Eles, Zebo Peng, Raimund Ubar, Maksim Jenihhin
    Test Time Minimization for Hybrid BIST of Core-Based Systems. [Citation Graph (0, 0)][DBLP]
    J. Comput. Sci. Technol., 2006, v:21, n:6, pp:907-912 [Journal]
  69. Luis Alejandro Cortés, Petru Eles, Zebo Peng
    Modeling and formal verification of embedded systems based on a Petri net representation. [Citation Graph (0, 0)][DBLP]
    Journal of Systems Architecture, 2003, v:49, n:12-15, pp:571-598 [Journal]
  70. Paul Pop, Petru Eles, Zebo Peng
    Schedulability-Driven Communication Synthesis for Time Triggered Embedded Systems. [Citation Graph (0, 0)][DBLP]
    Real-Time Systems, 2004, v:26, n:3, pp:297-325 [Journal]
  71. Marcus T. Schmitz, Bashir M. Al-Hashimi, Petru Eles
    Cosynthesis of energy-efficient multimode embedded systems with consideration of mode-execution probabilities. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:2, pp:153-169 [Journal]
  72. Paul Pop, Petru Eles, Zebo Peng
    Schedulability-driven frame packing for multicluster distributed embedded systems. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Embedded Comput. Syst., 2005, v:4, n:1, pp:112-140 [Journal]
  73. Mauricio Varea, Bashir M. Al-Hashimi, Luis Alejandro Cortés, Petru Eles, Zebo Peng
    Dual Flow Nets: Modeling the control/data-flow relation in embedded systems. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Embedded Comput. Syst., 2006, v:5, n:1, pp:54-81 [Journal]
  74. Marcus T. Schmitz, Bashir M. Al-Hashimi, Petru Eles
    Iterative schedule optimization for voltage scalable distributed embedded systems. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Embedded Comput. Syst., 2004, v:3, n:1, pp:182-217 [Journal]
  75. Sorin Manolache, Petru Eles, Zebo Peng
    Schedulability analysis of applications with stochastic task execution times. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Embedded Comput. Syst., 2004, v:3, n:4, pp:706-735 [Journal]
  76. Paul Pop, Petru Eles, Zebo Peng, Traian Pop
    Analysis and optimization of distributed real-time embedded systems. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2006, v:11, n:3, pp:593-625 [Journal]
  77. Paul Pop, Petru Eles, Zebo Peng, Traian Pop
    Scheduling and mapping in an incremental design methodology for distributed real-time embedded systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2004, v:12, n:8, pp:793-811 [Journal]
  78. Luis Alejandro Cortés, Petru Eles, Zebo Peng
    Quasi-Static Assignment of Voltages and Optional Cycles in Imprecise-Computation Systems With Energy Considerations. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:10, pp:1117-1129 [Journal]
  79. Traian Pop, Paul Pop, Petru Eles, Zebo Peng
    Bus access optimisation for FlexRay-based distributed embedded systems. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:51-56 [Conf]
  80. Anders Larsson, Erik Larsson, Petru Eles, Zebo Peng
    Optimized integration of test compression and sharing for SOC testing. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:207-212 [Conf]
  81. Erik Larsson, Mehdi Amirijoo, Daniel Karlsson, Petru Eles
    What impacts course evaluation? [Citation Graph (0, 0)][DBLP]
    ITiCSE, 2007, pp:333- [Conf]
  82. Sorin Manolache, Petru Eles, Zebo Peng
    Fault-aware Communication Mapping for NoCs with Guaranteed Latency. [Citation Graph (0, 0)][DBLP]
    International Journal of Parallel Programming, 2007, v:35, n:2, pp:125-156 [Journal]
  83. Alexandru Andrei, Petru Eles, Zebo Peng, Marcus T. Schmitz, Bashir M. Al-Hashimi
    Energy Optimization of Multiprocessor Systems on Chip by Voltage Selection. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:3, pp:262-275 [Journal]
  84. Petru Eles, Alex Doboli, Paul Pop, Zebo Peng
    Scheduling with bus access optimization for distributed embedded systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2000, v:8, n:5, pp:472-491 [Journal]

  85. Scheduling and voltage scaling for energy/reliability trade-offs in fault-tolerant time-triggered embedded systems. [Citation Graph (, )][DBLP]


  86. A standby-sparing technique with low energy-overhead for fault-tolerant hard real-time systems. [Citation Graph (, )][DBLP]


  87. On-line thermal aware dynamic voltage scaling for energy optimization with frequency/temperature dependency consideration. [Citation Graph (, )][DBLP]


  88. Quality-driven synthesis of embedded multi-mode control systems. [Citation Graph (, )][DBLP]


  89. Test-Architecture Optimization and Test Scheduling for SOCs with Core-Level Expansion of Compressed Test Patterns. [Citation Graph (, )][DBLP]


  90. Synthesis of Fault-Tolerant Embedded Systems. [Citation Graph (, )][DBLP]


  91. A Simulation Methodology for Worst-Case Response Time Estimation of Distributed Real-Time Systems. [Citation Graph (, )][DBLP]


  92. Scheduling of Fault-Tolerant Embedded Systems with Soft and Hard Timing Constraints. [Citation Graph (, )][DBLP]


  93. Temperature-Aware Voltage Selection for Energy Optimization. [Citation Graph (, )][DBLP]


  94. Integrated scheduling and synthesis of control applications on distributed embedded systems. [Citation Graph (, )][DBLP]


  95. Analysis and optimization of fault-tolerant embedded systems with hardened processors. [Citation Graph (, )][DBLP]


  96. Temperature-aware idle time distribution for energy optimization with dynamic voltage scaling. [Citation Graph (, )][DBLP]


  97. Multi-temperature testing for core-based system-on-chip. [Citation Graph (, )][DBLP]


  98. Temperature-Aware Task Mapping for Energy Optimization with Dynamic Voltage Scaling. [Citation Graph (, )][DBLP]


  99. Synthesis of Flexible Fault-Tolerant Schedules with Preemption for Mixed Soft and Hard Real-Time Systems. [Citation Graph (, )][DBLP]


  100. Thermal-Aware Test Scheduling for Core-Based SoC in an Abort-on-First-Fail Test Environment. [Citation Graph (, )][DBLP]


  101. Timing Analysis of the FlexRay Communication Protocol. [Citation Graph (, )][DBLP]


  102. Schedulability analysis for systems with data and control dependencies. [Citation Graph (, )][DBLP]


  103. 2009 IEEE/ACM/IFIP 7th workshop on embedded systems for Real-Time multimedia (ESTIMedia 2009). [Citation Graph (, )][DBLP]


  104. Timing constraint specification and synthesis in behavioral VHDL. [Citation Graph (, )][DBLP]


  105. Synthesis of VHDL concurrent processes. [Citation Graph (, )][DBLP]


  106. Immune Genetic Algorithms for Optimization of Task Priorities and FlexRay Frame Identifiers. [Citation Graph (, )][DBLP]


  107. Bus Access Optimization for Predictable Implementation of Real-Time Applications on Multiprocessor Systems-on-Chip. [Citation Graph (, )][DBLP]


  108. Predictable Implementation of Real-Time Applications on Multiprocessor Systems-on-Chip. [Citation Graph (, )][DBLP]


  109. Predictable Implementation of Real-Time Applications on Multiprocessor Systems on Chip. [Citation Graph (, )][DBLP]


  110. Transactor-based Formal Verification of Real-time Embedded Systems. [Citation Graph (, )][DBLP]


  111. A Formal Verification Approach for IP-based Designs. [Citation Graph (, )][DBLP]


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