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Shashi Kumar: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Maurizio Palesi, Rickard Holsmark, Shashi Kumar, Vincenzo Catania
    A methodology for design of application specific deadlock-free routing algorithms for NoC systems. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2006, pp:142-147 [Conf]
  2. Ahmed Hemani, Thomas Meincke, Shashi Kumar, Adam Postula, Thomas Olsson, Peter Nilsson, Johnny Öberg, Peeter Ellervee, Dan Lundqvist
    Lowering Power Consumption in Clock by Using Globally Asynchronous Locally Synchronous Design Style. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:873-878 [Conf]
  3. Axel Jantsch, Shashi Kumar, Ahmed Hemani
    The Rugby Model: A Conceptual Frame for the Study of Modelling, Analysis and Synthesis Concepts of Electronic Systems. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:256-262 [Conf]
  4. Tang Lei, Shashi Kumar
    A Two-step Genetic Algorithm for Mapping Task Graphs to a Network on Chip Architecture. [Citation Graph (0, 0)][DBLP]
    DSD, 2003, pp:180-189 [Conf]
  5. Rickard Holsmark, Maurizio Palesi, Shashi Kumar
    Deadlock Free Routing Algorithms for Mesh Topology NoC Systems with Regions. [Citation Graph (0, 0)][DBLP]
    DSD, 2006, pp:696-703 [Conf]
  6. Tomas Bengtsson, Artur Jutman, Shashi Kumar, Raimund Ubar, Zebo Peng
    Off-Line Testing of Delay Faults in NoC Interconnects. [Citation Graph (0, 0)][DBLP]
    DSD, 2006, pp:677-680 [Conf]
  7. Sushil Chandra Jain, Anshul Kumar, Shashi Kumar
    Efficient Embedding of Partitioned Circuits onto Multi-FPGA Boards. [Citation Graph (0, 0)][DBLP]
    FPL, 2000, pp:201-210 [Conf]
  8. Daniel Andreasson, Shashi Kumar
    Slack-time aware routing in NoC systems. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2353-2356 [Conf]
  9. Thomas Meincke, Ahmed Hemani, Shashi Kumar, Peeter Ellervee, Johnny Öberg, Thomas Olsson, Peter Nilsson, Dan Lindqvist, Hannu Tenhunen
    Globally asynchronous locally synchronous architecture for large high-performance ASICs. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 1999, pp:512-515 [Conf]
  10. Shashi Kumar, Axel Jantsch, Mikael Millberg, Johnny Öberg, Juha-Pekka Soininen, Martti Forsell, Kari Tiensyrjä, Ahmed Hemani
    A Network on Chip Architecture and Design Methodology. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2002, pp:117-124 [Conf]
  11. Sushil Chandra Jain, Anshul Kumar, Shashi Kumar
    Hybrid Multi-FPGA Board Evaluation by Limiting Multi-Hop Routing. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2002, pp:66-0 [Conf]
  12. Maurizio Palesi, Shashi Kumar, Rickard Holsmark
    A Method for Router Table Compression for Application Specific Routing in Mesh Topology NoC Architectures. [Citation Graph (0, 0)][DBLP]
    SAMOS, 2006, pp:373-384 [Conf]
  13. Tang Lei, Shashi Kumar
    Algorithms and Tools for Network on Chip Based System Design. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2003, pp:163-168 [Conf]
  14. Rickard Holsmark, Magnus Högberg, Shashi Kumar
    Modelling and Evaluation of a Network on Chip Architecture Using SDL. [Citation Graph (0, 0)][DBLP]
    SDL Forum, 2003, pp:166-182 [Conf]
  15. Gaurav Aggarwal, Nitin Thaper, Kamal Aggarwal, M. Balakrishnan, Shashi Kumar
    A Novel Reconfigurable Co-Processor Architecture. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:370-375 [Conf]
  16. C. S. Ajay, M. Balakrishnan, D. Harikrishna, M. Karunakaran, Anshul Kumar, Shashi Kumar, V. Mudgil, A. R. Naseer
    High Level Design Experiences with IDEAS. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1993, pp:110- [Conf]
  17. Sitanshu Jain, M. Balakrishnan, Anshul Kumar, Shashi Kumar
    Speeding Up Program Execution Using Reconfigurable Hardware and a Hardware Function Library. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1998, pp:400-405 [Conf]
  18. Sushil Chandra Jain, Shashi Kumar, Anshul Kumar
    Evaluation of Various Routing Architectures for Multi-FPGA Boards. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2000, pp:262-267 [Conf]
  19. Mikael Millberg, Erland Nilsson, Rikard Thid, Shashi Kumar, Axel Jantsch
    The Nostrum Backbone - a Communication Protocol Stack for Networks on Chip. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2004, pp:693-696 [Conf]
  20. Aviral Shrivastava, Mohit Kumar, Sanjiv Kapoor, Shashi Kumar, M. Balakrishnan
    Optimal Hardware/Software Partitioning for Concurrent Specification Using Dynamic Programming. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2000, pp:110-113 [Conf]
  21. Juha-Pekka Soininen, Axel Jantsch, Martti Forsell, Antti Pelkonen, Jari Kreku, Shashi Kumar
    Extending Platform-Based Design to Network on Chip Systems. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:401-0 [Conf]
  22. B. M. Subraya, Anshul Kumar, Shashi Kumar
    An HOL based framework for design of correct high level synthesizers. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1995, pp:249-254 [Conf]
  23. Bengt Svantesson, Shashi Kumar, Ahmed Hemani
    A Methodology and Algorithms for Efficient Interprocess Communication Synthesis from System Description in SDL. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1998, pp:78-84 [Conf]
  24. Axel Jantsch, Shashi Kumar, Ahmed Hemani
    A Metamodel for Studying Concepts in Electronic System Design. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2000, v:17, n:3, pp:78-85 [Journal]
  25. Shashi Kumar, Sanjeev Kumar, Prakash, Ravi Shankar, M. K. Tiwari, Shashi Bhushan Kumar
    Prediction of flow stress for carbon steels using recurrent self-organizing neuro fuzzy networks. [Citation Graph (0, 0)][DBLP]
    Expert Syst. Appl., 2007, v:32, n:3, pp:777-788 [Journal]
  26. S. Harikumar, Shashi Kumar
    Iterative Deepening Multiobjective A. [Citation Graph (0, 0)][DBLP]
    Inf. Process. Lett., 1996, v:58, n:1, pp:11-15 [Journal]
  27. Maurizio Palesi, Shashi Kumar, Rickard Holsmark, Vincenzo Catania
    Exploiting Communication Concurrency for Efficient Deadlock Free Routing in Reconfigurable NoC Platforms. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2007, pp:1-8 [Conf]
  28. Rickard Holsmark, Shashi Kumar
    Corrections to Chen and Chiu's Fault Tolerant Routing Algorithm for Mesh Networks. [Citation Graph (0, 0)][DBLP]
    J. Inf. Sci. Eng., 2007, v:23, n:6, pp:1649-1662 [Journal]

  29. Efficient Application Specific Routing Algorithms for NoC Systems utilizing Partially Faulty Links. [Citation Graph (, )][DBLP]


  30. Distance Constrained Mapping to Support NoC Platforms Based on Source Routing. [Citation Graph (, )][DBLP]


  31. Enabling web services for Classification of Satellite Image. [Citation Graph (, )][DBLP]


  32. Design of Bandwidth Aware and Congestion Avoiding Efficient Routing Algorithms for Networks-on-Chip Platforms. [Citation Graph (, )][DBLP]


  33. HiRA: A methodology for deadlock free routing in hierarchical networks on chip. [Citation Graph (, )][DBLP]


  34. Swarm Intelligence Inspired Classifiers in Comparison with Fuzzy and Rough Classifiers: A Remote Sensing Approach. [Citation Graph (, )][DBLP]


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