Conferences in DBLP
Wayne Wolf , Burak Ozer , Tiehan Lv VLSI Systems for Embedded Video. [Citation Graph (0, 0)][DBLP ] Conf ] Alice Wang , Anantha Chandrakasan , Stephen V. Kosonocky Optimal Supply and Threshold Scaling for Subthreshold CMOS Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Asim Smailagic , Matthew Ettus System Design and Power Optimization for Mobile Computers. [Citation Graph (0, 0)][DBLP ] Conf ] Ismail Kadayif , Mahmut T. Kandemir , Narayanan Vijaykrishnan , Mary Jane Irwin Hardware-Software Co-Adaptation for Data-Intensive Embedded Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Ahmed M. Shams , Wendi Pan , Archana Chidanandan , Magdy A. Bayoumi A Low Power High Performance Distributed DCT Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Vikas Chandra , Herman Schmit Simultaneous Optimization of Driving Buffer and Routing Switch Sizes in an FPGA using an Iso-Area Approach. [Citation Graph (0, 0)][DBLP ] Conf ] Seong-Ook Jung , Ki-Wook Kim , Sung-Mo Kang Optimal Timing for Skew-Tolerant High-Speed Domino Logic. [Citation Graph (0, 0)][DBLP ] Conf ] Mitchell A. Thornton , Rolf Drechsler , D. Michael Miller Multi-Output Timed Shannon Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Adnan Abdul-Aziz Gutub , Alexandre F. Tenca , Çetin Kaya Koç Scalable VLSI Architecture for GF(p) Montgomery Modular Inverse Computation. [Citation Graph (0, 0)][DBLP ] Conf ] David Duarte , Narayanan Vijaykrishnan , Mary Jane Irwin Impact of Technology Scaling in the Clock System Power. [Citation Graph (0, 0)][DBLP ] Conf ] Saraju P. Mohanty , N. Ranganathan , Vamsi Krishna Datapath Scheduling using Dynamic Frequency Clocking. [Citation Graph (0, 0)][DBLP ] Conf ] Kaveh Shakeri , James D. Meindl Temperature Variable Supply Voltage for Power Reduction. [Citation Graph (0, 0)][DBLP ] Conf ] Suvodeep Gupta , Srinivas Katkoori Force-Directed Scheduling for Dynamic Power Optimization. [Citation Graph (0, 0)][DBLP ] Conf ] J. W. Bruce , Mitchell A. Thornton , L. Shivakumaraiah , P. S. Kokate , X. Li Efficient Adder Circuits Based on a Conservative Reversible Logic Gate. [Citation Graph (0, 0)][DBLP ] Conf ] Mohamed A. Elgamel , Tarek Darwish , Magdy A. Bayoumi Noise Tolerant Low Power Dynamic TSPCL D Flip-Flops. [Citation Graph (0, 0)][DBLP ] Conf ] Naotaka Ohsawa , Masanori Hariyama , Michitaka Kameyama High-Performance Field Programmable VLSI Processor Based on a Direct Allocation of a Control/Data Flow Graph. [Citation Graph (0, 0)][DBLP ] Conf ] Shiuh-Rong Huang , Lan-Rong Dung VLSI Implementation for MAC-Level DWT Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Scott C. Smith Speedup of Self-Timed Digital Systems Using Early Completion. [Citation Graph (0, 0)][DBLP ] Conf ] Shashi Kumar , Axel Jantsch , Mikael Millberg , Johnny Öberg , Juha-Pekka Soininen , Martti Forsell , Kari Tiensyrjä , Ahmed Hemani A Network on Chip Architecture and Design Methodology. [Citation Graph (0, 0)][DBLP ] Conf ] Henry Y. H. Chuang , David P. Birch , Li-Chang Liu , Jong-Chih Chien , Steven P. Levitan , Ching-Chung Li A High Speed Shift-Invariant Wavelet Transform Chip for Video Compression. [Citation Graph (0, 0)][DBLP ] Conf ] Ingmar Neumann , Kolja Sulimma , Wolfgang Kunz Accelerating Retiming Under the Coupled-Edge Timing Model. [Citation Graph (0, 0)][DBLP ] Conf ] Anil Bahuman , Benjamin Bishop , Khaled Rasheed Automated Synthesis of Standard Cells using Genetic Algorithms. [Citation Graph (0, 0)][DBLP ] Conf ] Markus Wedler , Dominik Stoffel , Wolfgang Kunz Improving Structural FSM Traversal by Constraint-Satisfying Logic Simulation. [Citation Graph (0, 0)][DBLP ] Conf ] Bassam Shaer , Khaled Dib An Efficient Partitioning Algorithm of Combinational CMOS Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Srdjan Dragic , Martin Margala A 1.2V Built-In Architecture for High Frequency On-Line Iddq/delta Iddq Test. [Citation Graph (0, 0)][DBLP ] Conf ] 