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Publications of Author

1. Louis Scheffer
   Physical CAD changes to incorporate design for lithography and manufacturability. [Citation Graph (0, 0)][DBLP]
   ASP-DAC, 2004, pp:768-773 [Conf]
   
2. Raul Camposano, Jacob Greidinger, Patrick Groeneveld, Michael Jackson, Lawrence T. Pileggi, Louis Scheffer
   Design closure (panel session): hope or hype? [Citation Graph (0, 0)][DBLP]
   DAC, 2000, pp:176-177 [Conf]
   
3. Richard Goldman, Kurt Keutzer, Clive Bittlestone, Ahsan Bootehsaz, Shekhar Y. Borkar, E. Chen, Louis Scheffer, Chandramouli Visweswariah
   Is statistical timing statistically significant? [Citation Graph (0, 0)][DBLP]
   DAC, 2004, pp:498- [Conf]
   
4. Andrew B. Kahng, Shekhar Borkar, John Cohn, Antun Domic, Patrick Groeneveld, Louis Scheffer, Jean-Pierre Schoellkopf
   Nanometer design: place your bets. [Citation Graph (0, 0)][DBLP]
   DAC, 2003, pp:546-547 [Conf]
   
5. Andrew B. Kahng, Bing J. Sheu, Nancy Nettleton, John M. Cohn, Shekhar Borkar, Louis Scheffer, Ed Cheng, Sang Wang
   Panel: Is Nanometer Design Under Control? [Citation Graph (0, 0)][DBLP]
   DAC, 2001, pp:591-592 [Conf]
   
6. Hsiao-Ping Tseng, Louis Scheffer, Carl Sechen
   Timing and Crosstalk Driven Area Routing. [Citation Graph (0, 0)][DBLP]
   DAC, 1998, pp:378-381 [Conf]
   
7. Louis Scheffer, Ronny Soetarman
   Hierarchical analysis of IC artwork with user defined abstraction rules. [Citation Graph (0, 0)][DBLP]
   DAC, 1985, pp:293-298 [Conf]
   
8. Louis Scheffer
   Methodologies and Tools for Pipelined On-Chip Interconnect. [Citation Graph (0, 0)][DBLP]
   ICCD, 2002, pp:152-157 [Conf]
   
9. Desmond Kirkpatrick, Pete Osler, Louis Scheffer, Prashant Saxena, Dennis Sylvester
   The great interconnect buffering debate: are you a chicken or an ostrich? [Citation Graph (0, 0)][DBLP]
   ISPD, 2004, pp:61- [Conf]
   
10. Louis Scheffer
    A roadmap of CAD tool changes for sub-micron interconnect problems. [Citation Graph (0, 0)][DBLP]
    ISPD, 1997, pp:104-109 [Conf]
    
11. Louis Scheffer
    Signal Integrity and Power Supply Network Analysis of Deep SubMicron Chips. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2003, pp:194- [Conf]
    
12. Louis Scheffer
    An overview of on-chip interconnect variation. [Citation Graph (0, 0)][DBLP]
    SLIP, 2006, pp:27-28 [Conf]
    
13. Louis Scheffer, Eric Nequist
    Why interconnect prediction doesn't work. [Citation Graph (0, 0)][DBLP]
    SLIP, 2000, pp:139-144 [Conf]
    
14. Louis Scheffer
    Explicit computation of performance as a function of process variation. [Citation Graph (0, 0)][DBLP]
    Timing Issues in the Specification and Synthesis of Digital Systems, 2002, pp:1-8 [Conf]
    
15. Louis Scheffer
    Some conditions under which hierarchical verification is O(N). [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:5, pp:643-646 [Journal]
    
16. Hsiao-Ping Tseng, Louis Scheffer, Carl Sechen
    Timing- and crosstalk-driven area routing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:4, pp:528-544 [Journal]
    
17. Louis Scheffer
    CAD Implications of New Interconnect Technologies. [Citation Graph (0, 0)][DBLP]
    DAC, 2007, pp:576-581 [Conf]
    
18. David Cross, Eric Nequist, Louis Scheffer
    A DFM aware, space based router. [Citation Graph (0, 0)][DBLP]
    ISPD, 2007, pp:171-172 [Conf]
    
19. Louis Scheffer, Lars Liebmann, Riko Rakojcic, David White
    Rules vs tools: what's the right way to address IC manufacturing complexity? [Citation Graph (0, 0)][DBLP]
    ISPD, 2007, pp:75-76 [Conf]
    
20. Igor L. Markov, Louis Scheffer, Dirk Stroobandt
    Special issue on System-Level Interconnect Prediction. [Citation Graph (0, 0)][DBLP]
    Integration, 2007, v:40, n:4, pp:381- [Journal]
    
21. 
    Physical design of biological systems. [Citation Graph (, )][DBLP]