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Tatsuo Higuchi: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Takafumi Aoki, Hiroaki Amada, Tatsuo Higuchi
    Real/Complex Reconfigurable Arithmetic Using Redundant Complex Number Systems. [Citation Graph (0, 0)][DBLP]
    IEEE Symposium on Computer Arithmetic, 1997, pp:200-207 [Conf]
  2. Naofumi Homma, Takafumi Aoki, Tatsuo Higuchi
    Multiplier Block Synthesis Using Evolutionary Graph Generation. [Citation Graph (0, 0)][DBLP]
    Evolvable Hardware, 2004, pp:79-82 [Conf]
  3. Shinichi Shionoya, Takafumi Aoki, Tatsuo Higuchi
    Multiwave Interconnection Networks for MCM-based Parallel Processing. [Citation Graph (0, 0)][DBLP]
    Euro-Par, 1995, pp:593-607 [Conf]
  4. Hiroshi Nakajima, Koji Kobayashi, Makoto Morikawa, Atsushi Katsumata, Koichi Ito, Takafumi Aoki, Tatsuo Higuchi
    Fast and Robust Fingerprint Identification Algorithm and Its Application to Residential Access Controller. [Citation Graph (0, 0)][DBLP]
    ICB, 2006, pp:326-333 [Conf]
  5. Koichi Ito, Ayumi Morita, Takafumi Aoki, Hiroshi Nakajima, Koji Kobayashi, Tatsuo Higuchi
    A Fingerprint Recognition Algorithm Combining Phase-Based Image Matching and Feature-Based Matching. [Citation Graph (0, 0)][DBLP]
    ICB, 2006, pp:316-325 [Conf]
  6. Somchai Kittichaikoonkit, Michitaka Kameyama, Tatsuo Higuchi
    High-Performance VLSI Processor for Robot Inverse Dynamics Computation. [Citation Graph (0, 0)][DBLP]
    ICCD, 1991, pp:608-611 [Conf]
  7. Masayuki Kawamata, Jun Imakubo, Tatsuo Higuchi
    Optimal Design Method of 2-D IIR Digital Filters Based on a Simple Genetic Algorithm. [Citation Graph (0, 0)][DBLP]
    ICIP (1), 1994, pp:780-784 [Conf]
  8. Masayuki Kawamata, Masaki Nagahisa, Tatsuo Higuchi
    Multi-resolution Tree Search for Iterated Transformation Theory-Based Coding. [Citation Graph (0, 0)][DBLP]
    ICIP (3), 1994, pp:137-141 [Conf]
  9. Young-Ho Lee, Masayuki Kawamata, Tatsuo Higuchi
    Design of 2-D state-space digital filters with powers-of-two coefficients based on a genetic algorithm. [Citation Graph (0, 0)][DBLP]
    ICIP, 1995, pp:2133-2136 [Conf]
  10. Koichi Ito, Ayumi Morita, Takafumi Aoki, Tatsuo Higuchi, Hiroshi Nakajima, Koji Kobayashi
    A fingerprint recognition algorithm using phase-based image matching for low-quality fingerprints. [Citation Graph (0, 0)][DBLP]
    ICIP (2), 2005, pp:33-36 [Conf]
  11. Naofumi Homma, Takafumi Aoki, Makoto Motegi, Tatsuo Higuchi
    A framework of evolutionary graph generation system and its application to circuit synthesis. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:201-204 [Conf]
  12. Naofumi Homma, Jun Sakiyama, Taihei Wakamatsu, Takafumi Aoki, Tatsuo Higuchi
    A systematic approach for analyzing fast addition algorithms using counter tree diagrams. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2004, pp:197-200 [Conf]
  13. Yasushi Iwata, Masayuki Kawamata, Tatsuo Higuchi
    Design of Fine Grain VLSI Array Processor for Real-time 2-D Digital Filtering. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1559-1562 [Conf]
  14. Koichi Ito, Takafumi Aoki, Tatsuo Higuchi
    Design of a digital reaction-diffusion system for restoring blurred fingerprint images. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2003, pp:77-80 [Conf]
  15. Masayuki Kawamata, Eiichiro Kawakami, Tatsuo Higuchi
    Realization of lattice-form separable-denominator 2D adaptive filters. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:295-298 [Conf]
  16. Naofumi Homma, Takafumi Aoki, Tatsuo Higuchi
    Evolutionary graph generation system with transmigration capability for arithmetic circuit design. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:171-174 [Conf]
  17. Takafumi Aoki, Tatsuo Higuchi
    Impact of Interconnection-Free Biomolecular Computing. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1993, pp:271-276 [Conf]
  18. Takafumi Aoki, Tatsuo Higuchi
    Set-Valued Logic Circuits for Next Generation VLSI Architectures. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1998, pp:140-147 [Conf]
  19. Takafumi Aoki, Ken-ichi Hoshi, Tatsuo Higuchi
    Redundant Complex Arithmetic and Its Application to Complex Multiplier Design. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1999, pp:200-207 [Conf]
  20. Takafumi Aoki, Michitaka Kameyama, Tatsuo Higuchi
    Design of Interconnection-Free Biomolecular Computing System. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1991, pp:173-180 [Conf]
  21. Takafumi Aoki, Kimihiko Nakazawa, Tatsuo Higuchi
    High-Radix Parallel VLSI Dividers without Using Quotient Digit Selection Tables. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2000, pp:345-0 [Conf]
  22. Satoshi Aragaki, Takahiro Hanyu, Tatsuo Higuchi
    A Multiple-Valued Content-Addressable Memory Using Logic-Value Conversion and Threshold Functions. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1993, pp:170-175 [Conf]
  23. Katsuhiko Degawa, Takafumi Aoki, Tatsuo Higuchi
    A Field-Programmable Digital Filter Chip Using Multiple-Valued Current-Mode Logic. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2003, pp:213-220 [Conf]
  24. Katsuhiko Degawa, Takafumi Aoki, Tatsuo Higuchi, Hiroshi Inokawa, Katsuhiko Nishiguchi, Yasuo Takahashi
    A High-Density Ternary Content-Addressable Memory Using Single-Electron Transistors. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2006, pp:19- [Conf]
  25. Katsuhiko Degawa, Takafumi Aoki, Tatsuo Higuchi, Hiroshi Inokawa, Yasuo Takahashi
    A Single-Electron-Transistor Logic Gate Family and Its Application - Part I: Basic Components for Binary, Multiple-Valued and Mixed-Mode Logic. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2004, pp:262-268 [Conf]
  26. Katsuhiko Degawa, Takafumi Aoki, Hiroshi Inokawa, Tatsuo Higuchi, Yasuo Takahashi
    A Two-Bit-per-Cell Content-Addressable Memory Using Single-Electron Transistors. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2005, pp:32-38 [Conf]
  27. Takahiro Hanyu, Tatsuo Higuchi
    Design of a High-Density Multiple-Valued Content-Addressable Memory Based on Floating-Gate MOS Devices. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1990, pp:18-23 [Conf]
  28. Takahiro Hanyu, Tatsuo Higuchi
    A Floating-Gate-MOS-Based Multiple-Valued Associative Memory. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1991, pp:24-31 [Conf]
  29. Takahiro Hanyu, Yasushi Kojima, Tatsuo Higuchi
    A Multiple-Valued Logic Artay VLSI Based on Two-Transistor Delta Literal Circuit and Its Application to Real-Time Reasoning Systems. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1991, pp:16-23 [Conf]
  30. Takahiro Hanyu, Kouichi Takeda, Tatsuo Higuchi
    Design of a Multiple-Valued Rule-Programmable Matching VLSI Chip for Real-Time Rule-Based Systems. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1992, pp:274-281 [Conf]
  31. Masahiko Hiratsuka, Takafumi Aoki, Tatsuo Higuchi
    A Model of Reaction-Diffusion Cellular Automata for Massively Parallel Molecular Computing. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2001, pp:247-252 [Conf]
  32. Masahiko Hiratsuka, Takafumi Aoki, Tatsuo Higuchi
    Enzyme Transistor Circuits for Biomolecular Computing. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1997, pp:47-0 [Conf]
  33. Naofumi Homma, Takafumi Aoki, Tatsuo Higuchi
    Algorithm-level interpretation of fast adder structures in binary and multiple-valued logic. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2006, pp:2- [Conf]
  34. Makoto Honda, Michitaka Kameyama, Tatsuo Higuchi
    Residue Arithmetic Based Multiple-Valued VLSI Image Processor. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1992, pp:330-336 [Conf]
  35. Hiroshi Inokawa, Yasuo Takahashi, Katsuhiko Degawa, Takafumi Aoki, Tatsuo Higuchi
    A Single-Electron-Transistor Logic Gate Family and Its Application - Part II: Design and Simulation of a 7-3 Parallel Counter with Linear Summation and Multiple-Valued Latch Functions. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2004, pp:269-274 [Conf]
  36. Kazuya Ishida, Naofumi Homma, Takafumi Aoki, Tatsuo Higuchi
    Design and Verification of Parallel Multipliers Using Arithmetic Description Language: ARITH. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2004, pp:334-339 [Conf]
  37. Michitaka Kameyama, Masahiro Nomura, Tatsuo Higuchi
    Modular Design of Multiple-Valued Arithmetic VLSI System Using Signed-Digit Number System. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1990, pp:355-362 [Conf]
  38. Shuichi Maeda, Takafumi Aoki, Tatsuo Higuchi
    Set-Valued Logic Networks Based on Optical Wavelength Multiplexing. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1992, pp:282-290 [Conf]
  39. Masanori Natsui, Takafumi Aoki, Tatsuo Higuchi
    Synthesis of Multiple-Valued Arithmetic Circuits Using Evolutionary Graph Generation. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2001, pp:253-258 [Conf]
  40. Masanori Natsui, Takafumi Aoki, Tatsuo Higuchi
    Parallel Evolutionary Graph Synthesis on a PC Cluster and Its Application to Multiple-Valued Circuit Synthesis. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2002, pp:96-0 [Conf]
  41. Y. Ohi, Takafumi Aoki, Tatsuo Higuchi
    Redundant Complex Number Systems. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1995, pp:14-19 [Conf]
  42. Jun Sakiyama, Takafumi Aoki, Tatsuo Higuchi
    Counter Tree Diagrams for Design and Analysis of Fast Addition Algorithms. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2003, pp:91-98 [Conf]
  43. S. Sakurai, Takafumi Aoki, Tatsuo Higuchi
    Wire-Free Computing Circuits Using Optical Wave-Casting. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1995, pp:8-13 [Conf]
  44. Takashi Takimoto, Takafumi Aoki, Tatsuo Higuchi
    Design of Multiplex Interconnection Networks for Massively Parallel Computing Systems. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1994, pp:231-238 [Conf]
  45. Saneaki Tamaki, Michitaka Kameyama, Tatsuo Higuchi
    Code Assignment Algorithm for Highly Parallel Multiple-Valued Combinatorial Circuits. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1992, pp:382-388 [Conf]
  46. Katsuhiko Shimabukuro, Michitaka Kameyama, Tatsuo Higuchi
    Design of a Multiple-Valued VLSI Processor for Digital Control. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1992, pp:322-329 [Conf]
  47. Yasushi Yuminaka, Takafumi Aoki, Tatsuo Higuchi
    Design of a Set Logic Network Based on Frequency Multiplexing and Its Applications to Image Processing. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1991, pp:8-15 [Conf]
  48. Yasushi Yuminaka, Takafumi Aoki, Tatsuo Higuchi
    Design of Set-Valued Logic Networks for Wave-Parallel Computing. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1993, pp:277-282 [Conf]
  49. Yasushi Yuminaka, Takafumi Aoki, Tatsuo Higuchi
    Design of Wave-Parallel Computing Circuits for Densely Connected Architectures. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1994, pp:207-214 [Conf]
  50. Yasushi Yuminaka, Osamu Katoh, Yoshisat Sasaki, Takafumi Aoki, Tatsuo Higuchi
    An Efficient Data Transmission Technique for VLSI Systems Based on Multiple-Valued Code-Division Multiple Access. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2000, pp:430-437 [Conf]
  51. Yasushi Yuminaka, Tatsuya Morishita, Takafumi Aoki, Tatsuo Higuchi
    Multiple-Valued Data Recovery Techniques for Band-Limited Channels in VLSI. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2002, pp:54-60 [Conf]
  52. Yasushi Yuminaka, Yoshisato Sasaki, Takafumi Aoki, Tatsuo Higuchi
    Wave-Parallel Computing Technique for Neural Networks Based on Amplitude-Modulated Waves. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1996, pp:210-215 [Conf]
  53. Yasushi Yuminaka, Yoshisat Sasaki, Takafumi Aoki, Tatsuo Higuchi
    Wave-Parallel Computing Systems using Multiple-Valued Pseudo-Orthogonal Sequences. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1998, pp:148-0 [Conf]
  54. Qiangfu Zhao, Tatsuo Higuchi
    Individual Evolutionary Algorithm and its Application to Learning of Nearest Neighbor Based MLP. [Citation Graph (0, 0)][DBLP]
    IWANN, 1995, pp:396-403 [Conf]
  55. Yoshiko Yasuda, Shinichi Kawamoto, Atsushi Ebata, Jun Okitsu, Tatsuo Higuchi
    Concept and Evaluation of X-NAS: A Highly Scalable NAS System. [Citation Graph (0, 0)][DBLP]
    IEEE Symposium on Mass Storage Systems, 2003, pp:219-0 [Conf]
  56. Makoto Motegi, Naofumi Homma, Takafumi Aoki, Tatsuo Higuchi
    Evolutionary Graph Generation System and Its Application to Bit-Serial Arithmetic Circuit Synthesis. [Citation Graph (0, 0)][DBLP]
    PPSN, 2002, pp:831-840 [Conf]
  57. Masanori Natsui, Naofumi Homma, Takafumi Aoki, Tatsuo Higuchi
    Topology-Oriented Design of Analog Circuits Based on Evolutionary Graph Generation. [Citation Graph (0, 0)][DBLP]
    PPSN, 2004, pp:342-351 [Conf]
  58. Takafumi Aoki, Naofumi Homma, Tatsuo Higuchi
    Evolutionary Synthesis of Arithmetic Circuit Structures. [Citation Graph (0, 0)][DBLP]
    Artif. Intell. Rev., 2003, v:20, n:3-4, pp:199-232 [Journal]
  59. Takafumi Aoki, Michitaka Kameyama, Tatsuo Higuchi
    Interconnection-Free Biomolecular Computing. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 1992, v:25, n:11, pp:41-50 [Journal]
  60. Michitaka Kameyama, Shoji Kawahito, Tatsuo Higuchi
    A Multiplier Chip with Multiple-Valued Bidirectional Current-Mode Logic Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 1988, v:21, n:4, pp:43-56 [Journal]
  61. Qiangfu Zhao, Tatsuo Higuchi
    Efficient learning of NN-MLP based on individual evolutionary algorithm. [Citation Graph (0, 0)][DBLP]
    Neurocomputing, 1996, v:13, n:2-4, pp:201-215 [Journal]
  62. Qiangfu Zhao, Tatsuo Higuchi
    Minimization of nearest neighbor classifiers based on individual evolutionary algorithm. [Citation Graph (0, 0)][DBLP]
    Pattern Recognition Letters, 1996, v:17, n:2, pp:125-131 [Journal]
  63. Tatsuo Higuchi, Michitaka Kameyama
    Static-Hazard-Free T-Gate for Ternary Memory Element and Its Application to Ternary Counters. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1977, v:26, n:12, pp:1212-1221 [Journal]
  64. Michitaka Kameyama, Tatsuo Higuchi
    Synthesis of Multiple-Valued Logic Networks Based on Tree-Type Universal Logic Module. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1977, v:26, n:12, pp:1297-1302 [Journal]
  65. Shoji Kawahito, Makoto Ishida, Tetsuro Nakamura, Michitaka Kameyama, Tatsuo Higuchi
    High-Speed Area-Efficient Multiplier Design Using Multiple-Valued Current-Mode Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1994, v:43, n:1, pp:34-42 [Journal]
  66. Shoji Kawahito, Makoto Ishida, Tasuro Nakamura, Michitaka Kameyama, Tatsuo Higuchi
    Author's Reply. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1996, v:45, n:5, pp:639- [Journal]
  67. Dingjun Chen, Takafumi Aoki, Naofumi Homma, Toshiki Terasaki, Tatsuo Higuchi
    Graph-based evolutionary design of arithmetic circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Evolutionary Computation, 2002, v:6, n:1, pp:86-100 [Journal]
  68. Koichi Ito, Takafumi Aoki, Hiroshi Nakajima, Koji Kobayashi, Tatsuo Higuchi
    A Palmprint Recognition Algorithm using Phase-Based Image Matching. [Citation Graph (0, 0)][DBLP]
    ICIP, 2006, pp:2669-2672 [Conf]

  69. Application of symbolic computer algebra to arithmetic circuit verification. [Citation Graph (, )][DBLP]


  70. Arithmetic module generator with algorithm optimization capability. [Citation Graph (, )][DBLP]


  71. High-Level Design of Multiple-Valued Arithmetic Circuits Based on Arithmetic Description Language. [Citation Graph (, )][DBLP]


  72. Algorithm-Level Optimization of Multiple-Valued Arithmetic Circuits Using Counter Tree Diagrams. [Citation Graph (, )][DBLP]


  73. An On-line Backup Function for a Clustered NAS System (X-NAS). [Citation Graph (, )][DBLP]


  74. VLSI circuit design using an object-oriented framework of evolutionary graph generation system. [Citation Graph (, )][DBLP]


  75. An LVQ-based technique for human motion segmentation. [Citation Graph (, )][DBLP]


  76. Pixel-wise human motion segmentation using learning vector quantization. [Citation Graph (, )][DBLP]


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