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Patrick Groeneveld:
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Publications of Author
- Raul Camposano, Olivier Coudert, Patrick Groeneveld, Leon Stok, Ralph H. J. M. Otten
Timing closure: the solution and its problems. [Citation Graph (0, 0)][DBLP] ASP-DAC, 2000, pp:359-364 [Conf]
- Raul Camposano, Jacob Greidinger, Patrick Groeneveld, Michael Jackson, Lawrence T. Pileggi, Louis Scheffer
Design closure (panel session): hope or hype? [Citation Graph (0, 0)][DBLP] DAC, 2000, pp:176-177 [Conf]
- Andrew B. Kahng, Shekhar Borkar, John Cohn, Antun Domic, Patrick Groeneveld, Louis Scheffer, Jean-Pierre Schoellkopf
Nanometer design: place your bets. [Citation Graph (0, 0)][DBLP] DAC, 2003, pp:546-547 [Conf]
- Andrew B. Kahng, Ronald Collett, Patrick Groeneveld, Lavi Lev, Nancy Nettleton, Paul K. Rodman, Lambert van den Hoven
Tools or users: which is the bigger bottleneck? [Citation Graph (0, 0)][DBLP] DAC, 2002, pp:76-77 [Conf]
- Francky Catthoor, Andrea Cuomo, Grant Martin, Patrick Groeneveld, Rudy Lauwereins, Karen Maex, Patrick van de Steeg, Ron Wilson
How Can System-Level Design Solve the Interconnect Technology Scaling Problem? [Citation Graph (0, 0)][DBLP] DATE, 2004, pp:332-339 [Conf]
- Ralph H. J. M. Otten, Raul Camposano, Patrick Groeneveld
Design Automation for Deepsubmicron: Present and Future. [Citation Graph (0, 0)][DBLP] DATE, 2002, pp:650-659 [Conf]
- Rob A. Rutenbar, Olivier Coudert, Patrick Groeneveld, Jürgen Koehl, Scott Peterson, Vivek Raghavan, Naresh Soni
Automatic Hierarchical Design: Fantasy or Reality? (Panel). [Citation Graph (0, 0)][DBLP] ICCAD, 2001, pp:656-0 [Conf]
- Patrick Groeneveld
Physical Design Challenges for Billion Transistor Chips. [Citation Graph (0, 0)][DBLP] ICCD, 2002, pp:78-83 [Conf]
- Patrick Groeneveld, Jacob Greidinger, J. George Janac, Wilm E. Donath
The right floorplanning formulations for future chip implementation methodologies (panel discussion - title only). [Citation Graph (0, 0)][DBLP] ISPD, 2000, pp:214- [Conf]
- Jurjen Westra, Chris Bartels, Patrick Groeneveld
Probabilistic congestion prediction. [Citation Graph (0, 0)][DBLP] ISPD, 2004, pp:204-209 [Conf]
- Jurjen Westra, Patrick Groeneveld
Post-Placement Pin Optimiztion. [Citation Graph (0, 0)][DBLP] ISVLSI, 2005, pp:238-243 [Conf]
- Jurjen Westra, Patrick Groeneveld
Towards Integration of Quadratic Placement and Pin Assignment. [Citation Graph (0, 0)][DBLP] ISVLSI, 2005, pp:284-286 [Conf]
- Jurjen Westra, Patrick Groeneveld
Is probabilistic congestion estimation worthwhile? [Citation Graph (0, 0)][DBLP] SLIP, 2005, pp:99-106 [Conf]
- Patrick Groeneveld
A multiple layer contour-based gridless channel router. [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 1990, v:9, n:12, pp:1278-1288 [Journal]
- Chris Bartels, Jos Huisken, Kees Goossens, Patrick Groeneveld, Jef L. van Meerbergen
Comparison of An Æthereal Network on Chip and A Traditional Interconnect for A Multi-Processor DVB-T System on Chip. [Citation Graph (0, 0)][DBLP] VLSI-SoC, 2006, pp:80-85 [Conf]
Oil fields, hedge funds, and drugs. [Citation Graph (, )][DBLP]
Going with the flow: bridging the gap between theory and practice in physical design. [Citation Graph (, )][DBLP]
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