The SCEAS System
Navigation Menu

Search the dblp DataBase

Title:
Author:

Mehrdad Nourani: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Behnam Robatmili, Nasser Yazdani, Mehrdad Nourani
    NPSMT: A Simulation Environment for SMT Packet Processors. [Citation Graph (0, 0)][DBLP]
    ISCA PDCS, 2004, pp:151-156 [Conf]
  2. Mohammad Tehranipoor, Mehrdad Nourani, Nisar Ahmed
    Low Transition LFSR for BIST-Based Applications. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2005, pp:138-143 [Conf]
  3. Amir Attarha, Mehrdad Nourani
    Signal integrity fault analysis using reduced-order modeling. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:367-370 [Conf]
  4. Amir Attarha, Mehrdad Nourani, Carco Lucas
    Modeling and simulation of real defects using fuzzy logic. [Citation Graph (0, 0)][DBLP]
    DAC, 2000, pp:631-636 [Conf]
  5. Mehrdad Nourani, Amir Attarha
    Built-In Self-Test for Signal Integrity. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:792-797 [Conf]
  6. Mehrdad Nourani, Joan Carletta, Christos A. Papachristou
    Synthesis-for-testability of controller-datapath pairs that use gated clocks. [Citation Graph (0, 0)][DBLP]
    DAC, 2000, pp:613-618 [Conf]
  7. Mehrdad Nourani, Joan Carletta, Christos A. Papachristou
    A Scheme for Integrated Controller-Datapath Fault Testing. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:546-551 [Conf]
  8. Mehrdad Nourani, Christos A. Papachristou
    Move Frame Scheduling and Mixed Scheduling-Allocation for the Automated Synthesis of Digital Systems. [Citation Graph (0, 0)][DBLP]
    DAC, 1992, pp:99-105 [Conf]
  9. Mehrdad Nourani, Christos A. Papachristou
    A Layout Estimation Algorithm for RTL Datapaths. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:285-291 [Conf]
  10. Christos A. Papachristou, Haidar Harmanani, Mehrdad Nourani
    An Approach for Redesigning in Data Path Synthesis. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:419-423 [Conf]
  11. Christos A. Papachristou, F. Martin, Mehrdad Nourani
    Microprocessor Based Testing for Core-Based System on Chip. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:586-591 [Conf]
  12. Christos A. Papachristou, Mark Spining, Mehrdad Nourani
    An Effective Power Management Scheme for RTL Design Based on Multiple Clocks. [Citation Graph (0, 0)][DBLP]
    DAC, 1996, pp:337-342 [Conf]
  13. Nisar Ahmed, Mohammad H. Tehranipour, Mehrdad Nourani
    Extending JTAG for Testing Signal Integrity in SoCs. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10218-10223 [Conf]
  14. Joan Carletta, Mehrdad Nourani, Christos A. Papachristou
    Synthesis of Controllers for Full Testability of Integrated Datapath-Controller Pairs. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:278-282 [Conf]
  15. Joan Carletta, Christos A. Papachristou, Mehrdad Nourani
    Detecting Undetectable Controller Faults Using Power Analysis. [Citation Graph (0, 0)][DBLP]
    DATE, 2000, pp:723-728 [Conf]
  16. James Chin, Mehrdad Nourani
    SoC Test Scheduling with Power-Time Tradeoff and Hot Spot Avoidance. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:710-711 [Conf]
  17. Mehrdad Nourani, Christos A. Papachristou
    A Bypass Scheme for Core-Based System Fault Testing. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:979-980 [Conf]
  18. Mohammad H. Tehranipour, Mehrdad Nourani, Krishnendu Chakrabarty
    Nine-Coded Compression Technique with Application to Reduced Pin-Count Testing and Flexible On-Chip Decompression. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:1284-1289 [Conf]
  19. A. Amirabadi, Javid Jaffari, Ali Afzali-Kusha, Mehrdad Nourani, Ali Khaki-Firooz
    Leakage current reduction by new technique in standby mode. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2004, pp:158-161 [Conf]
  20. Mohammad J. Akhbarizadeh, Mehrdad Nourani, Rina Panigrahy, Samar Sharma
    High-Speed and Low-Power Network Search Engine Using Adaptive Block-Selection Scheme. [Citation Graph (0, 0)][DBLP]
    Hot Interconnects, 2005, pp:73-78 [Conf]
  21. Mohammad J. Akhbarizadeh, Mehrdad Nourani, Deepak S. Vijayasarathi, Poras T. Balsara
    PCAM: A Ternary CAM Optimized for Longest Prefix Matching Tasks. [Citation Graph (0, 0)][DBLP]
    ICCD, 2004, pp:6-11 [Conf]
  22. Mehrdad Nourani, James Chin
    Power-Time Tradeoff in Test Scheduling for SoCs. [Citation Graph (0, 0)][DBLP]
    ICCD, 2003, pp:548-553 [Conf]
  23. Mohammad H. Tehranipour, Nisar Ahmed, Mehrdad Nourani
    Multiple Transition Model and Enhanced Boundary Scan Architecture to Test Interconnects for Signal Integrity. [Citation Graph (0, 0)][DBLP]
    ICCD, 2003, pp:554-0 [Conf]
  24. Deepak S. Vijayasarathi, Mehrdad Nourani, Mohammad J. Akhbarizadeh, Poras T. Balsara
    Ripple-Precharge TCAM A Low-Power Solution for Network Search Engines. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:243-248 [Conf]
  25. Ali Abbasian, Safar Hatami, Ali Afzali-Kusha, Mehrdad Nourani, Carco Lucas
    Event-driven dynamic power management based on wavelet forecasting theory. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2004, pp:325-328 [Conf]
  26. Ali Abbasian, S. Rasouli, Ali Afzali-Kusha, Mehrdad Nourani
    No-race charge recycling complementary pass transistor logic (NCRCPL) for low power applications. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:289-292 [Conf]
  27. Nisar Ahmed, Mohammad H. Tehranipour, Dian Zhou, Mehrdad Nourani
    Frequency driven repeater insertion for deep submicron. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2004, pp:181-184 [Conf]
  28. A. Amirabadi, Y. Mortazavi, Nariman Moezzi Madani, Ali Afzali-Kusha, Mehrdad Nourani
    Domino logic with an efficient variable threshold voltage keeper. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1674-1677 [Conf]
  29. Morteza Gholipour, Hamid Shojaee, Ali Afzali-Kusha, Ahmad Khademzadeh, Mehrdad Nourani
    An efficient model for performance analysis of asynchronous pipeline design methods. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:5234-5237 [Conf]
  30. Mohammad H. Tehranipour, Mehrdad Nourani, Seid Mehdi Fakhraie, Ali Afzali-Kusha
    Systematic test program generation for SoC testing using embedded processor. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:541-544 [Conf]
  31. Nisar Ahmed, Mohammad H. Tehranipour, Mehrdad Nourani
    Low power pattern generation for BIST architecture. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2004, pp:689-692 [Conf]
  32. Mohammad H. Tehranipour, Mehrdad Nourani, Karim Arabi, Ali Afzali-Kusha
    Mixed RL-Huffman encoding for power reduction and data compression in scan test. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2004, pp:681-684 [Conf]
  33. Christos A. Papachristou, Mark Spining, Mehrdad Nourani
    A multiple clocking scheme for low power RTL design. [Citation Graph (0, 0)][DBLP]
    ISLPD, 1995, pp:27-32 [Conf]
  34. Amir Attarha, Mehrdad Nourani
    Testing interconnects for noise and skew in gigahertz SoCs. [Citation Graph (0, 0)][DBLP]
    ITC, 2001, pp:305-314 [Conf]
  35. Kendrick Baker, Mehrdad Nourani
    Interconnect Test Pattern Generation Algorithm For Meeting Device and Global SSO Limits With Safe Initial Vectors. [Citation Graph (0, 0)][DBLP]
    ITC, 2004, pp:163-172 [Conf]
  36. Mehrdad Nourani, Christos A. Papachristou
    An ILP formulation to optimize test access mechanism in system-on-chip testing. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:902-910 [Conf]
  37. Mohammad H. Tehranipour, Mehrdad Nourani
    Signal Integrity Loss in SoC's Interconnects: A Diagnosis Approach Using Embedded Microprocessor. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:1093-1102 [Conf]
  38. Amir Attarha, Mehrdad Nourani
    Built-In-Chip Testing of Voltage Overshoots in High-Speed SoCs. [Citation Graph (0, 0)][DBLP]
    VTS, 2001, pp:111-116 [Conf]
  39. Amir Attarha, Mehrdad Nourani
    Test Pattern Generation for Signal Integrity Faults on Long Interconnects. [Citation Graph (0, 0)][DBLP]
    VTS, 2002, pp:336-344 [Conf]
  40. Mehrdad Nourani, James Chin
    Testing High-Speed SoCs Using Low-Speed ATEs. [Citation Graph (0, 0)][DBLP]
    VTS, 2002, pp:133-138 [Conf]
  41. Mehrdad Nourani, Christos A. Papachristou
    Parallelism in Structural Fault Testing of Embedded Cores. [Citation Graph (0, 0)][DBLP]
    VTS, 1998, pp:15-21 [Conf]
  42. Mehrdad Nourani, Mohammad Tehranipoor, Nisar Ahmed
    Pattern Generation and Estimation for Power Supply Noise Analysis. [Citation Graph (0, 0)][DBLP]
    VTS, 2005, pp:439-444 [Conf]
  43. Mohammad H. Tehranipour, Nisar Ahmed, Mehrdad Nourani
    Testing SoC Interconnects for Signal Integrity Using Boundary Scan. [Citation Graph (0, 0)][DBLP]
    VTS, 2003, pp:158-172 [Conf]
  44. Mohammad J. Akhbarizadeh, Mehrdad Nourani, Cyrus Cantrell
    Prefix Segregation Scheme for a TCAM-Based IP Forwarding Engine. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2005, v:25, n:4, pp:48-63 [Journal]
  45. James Chin, Mehrdad Nourani
    FITS: An Integrated ILP-Based Test Scheduling Environment. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2005, v:54, n:12, pp:1598-1613 [Journal]
  46. Mohammad J. Akhbarizadeh, Mehrdad Nourani, Rina Panigrahy, Samar Sharma
    A TCAM-Based Parallel Architecture for High-Speed Packet Forwarding. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2007, v:56, n:1, pp:58-72 [Journal]
  47. Mohammad H. Tehranipour, Nisar Ahmed, Mehrdad Nourani
    Testing SoC interconnects for signal integrity using extended JTAG architecture. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:5, pp:800-811 [Journal]
  48. Mehrdad Nourani, Joan Carletta, Christos A. Papachristou
    Integrated test of interacting controllers and datapaths. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2001, v:6, n:3, pp:401-422 [Journal]
  49. Mehrdad Nourani, Mohammad H. Tehranipour
    RL-huffman encoding for test compression and power reduction in scan applications. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2005, v:10, n:1, pp:91-115 [Journal]
  50. Mohammad J. Akhbarizadeh, Mehrdad Nourani
    Hardware-based IP routing using partitioned lookup table. [Citation Graph (0, 0)][DBLP]
    IEEE/ACM Trans. Netw., 2005, v:13, n:4, pp:769-781 [Journal]
  51. Mohammad J. Akhbarizadeh, Mehrdad Nourani, Deepak S. Vijayasarathi, T. Balsara
    A nonredundant ternary CAM circuit for network search engines. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:3, pp:268-278 [Journal]
  52. Mohammad Tehranipoor, Mehrdad Nourani, Krishnendu Chakrabarty
    Nine-coded compression technique for testing embedded cores in SoCs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:6, pp:719-731 [Journal]
  53. Behnam Robatmili, Nasser Yazdani, Mehrdad Nourani
    Optimizing SMT processors for IP-packet processing. [Citation Graph (0, 0)][DBLP]
    Microprocessors and Microsystems, 2005, v:29, n:7, pp:337-349 [Journal]
  54. Mehrdad Nourani, Mohammad J. Akhbarizadeh
    Reconfigurable memory architecture for scalable IP forwarding engines. [Citation Graph (0, 0)][DBLP]
    Microprocessors and Microsystems, 2003, v:27, n:5-6, pp:253-263 [Journal]
  55. Miad Faezipour, Mehrdad Nourani
    A Customized TCAM Architecture for Multi-Match Packet Classification. [Citation Graph (0, 0)][DBLP]
    GLOBECOM, 2006, pp:- [Conf]
  56. A. Amirabadi, Ali Afzali-Kusha, Y. Mortazavi, Mehrdad Nourani
    Clock Delayed Domino Logic With Efficient Variable Threshold Voltage Keeper. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:2, pp:125-134 [Journal]
  57. Christos A. Papachristou, Mehrdad Nourani, Mark Spining
    A multiple clocking scheme for low-power RTL design. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1999, v:7, n:2, pp:266-276 [Journal]
  58. Mehrdad Nourani, Christos A. Papachristou
    Stability-based algorithms for high-level synthesis of digital ASICs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2000, v:8, n:4, pp:431-435 [Journal]
  59. Mehrdad Nourani, Christos A. Papachristou
    False path exclusion in delay analysis of RTL structures. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2002, v:10, n:1, pp:30-43 [Journal]

  60. Structural BIST insertion using behavioral test analysis. [Citation Graph (, )][DBLP]


  61. Reconfigurable Constraint Repetition Unit for Regular Expression Matching. [Citation Graph (, )][DBLP]


  62. Constraint Repetition Inspection for Regular Expression on FPGA. [Citation Graph (, )][DBLP]


  63. Distributed voting for fault-tolerant nanoscale systems. [Citation Graph (, )][DBLP]


  64. Reconfigurable CAM Architecture for Network Search Engines. [Citation Graph (, )][DBLP]


  65. Highly reliable A/D converter using analog voting. [Citation Graph (, )][DBLP]


  66. Regular Expression Matching for Reconfigurable Constraint Repetition Inspection. [Citation Graph (, )][DBLP]


  67. Testing On-Die Process Variation in Nanometer VLSI. [Citation Graph (, )][DBLP]


Search in 0.102secs, Finished in 0.105secs
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002