Conferences in DBLP
Walden C. Rhines Emerging Technologies Drive Domain-Specific Solutions. [Citation Graph (0, 0)][DBLP ] Conf ] Wojciech Maly New and Not-So-New Test Challenges of the Next Decade. [Citation Graph (0, 0)][DBLP ] Conf ] Peter Wohl , John A. Waicukauski Test Generation for Ultra-Large Circuits Using ATPG Constraints and Test-Pattern Templates. [Citation Graph (0, 0)][DBLP ] Conf ] Mitsuo Teramoto , Tomoo Fukazawa Test Pattern Generation for Circuits with Asynchronous Signals Based on Scan. [Citation Graph (0, 0)][DBLP ] Conf ] M. H. Konijnenburg , J. Th. van der Linden , A. J. van de Goor Accelerated Compact Test Set Generation for Three-State Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Fulvio Corno , Paolo Prinetto , Maurizio Rebaudengo , Matteo Sonza Reorda Comparing Topological, Symbolic and GA-based ATPGs: An Experimental Approach. [Citation Graph (0, 0)][DBLP ] Conf ] Yuejian Wu , Saman Adham BIST Fault Diagnosis in Scan-Based VLSI Environments. [Citation Graph (0, 0)][DBLP ] Conf ] Pieter M. Trouborst LFSR Reseeding as a Component of Board Level BIST. [Citation Graph (0, 0)][DBLP ] Conf ] Charles E. Stroud , Eric Lee , Srinivasa Konala , Miron Abramovici Using ILA Testing for BIST in FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Dimitris Gizopoulos , Antonis M. Paschalis , Yervant Zorian An Effective BIST Scheme for Datapaths. [Citation Graph (0, 0)][DBLP ] Conf ] Seiji Sasho , Teruhisa Sakata Four Multi Probing Test for 16 Bit DAC with Vertical Contact Probe Card. [Citation Graph (0, 0)][DBLP ] Conf ] Keith Lofstrom A Demonstration IC for the P1149.4 Mixed-Signal Test Standard. [Citation Graph (0, 0)][DBLP ] Conf ] Koji Asami Testing the Digital Modulation of PHS Devices. [Citation Graph (0, 0)][DBLP ] Conf ] Barry D. Kulp Testing and Characterizing Jitter in 100BASE-TX and 155.52 Mbit/S ATM Devices with a 1 Gsample/s AWG in an ATE System. [Citation Graph (0, 0)][DBLP ] Conf ] Kenji Isawa , Yoshihiro Hashimoto High-Speed IDDQ Measurement Circuit. [Citation Graph (0, 0)][DBLP ] Conf ] Solomon Max Extending Calibration Intervals. [Citation Graph (0, 0)][DBLP ] Conf ] Steven DeFoster , Dennis Karst , Matthew Peterson , Paul Sendelbach , Kirk Kottschade Manufacturing Test of Fiber Channel Communications Cards and Optical Subassemblies. [Citation Graph (0, 0)][DBLP ] Conf ] Bejoy G. Oomman , Wu-Tung Cheng , John A. Waicukauski A Universal Technique for Accelerating Simulation of Scan Test Patterns. [Citation Graph (0, 0)][DBLP ] Conf ] Elizabeth M. Rudnick , Janak H. Patel , Irith Pomeranz On Potential Fault Detection in Sequential Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Weiwei Mao , Ravi K. Gulati Improving Gate Level Fault Coverage by RTL Fault Grading. [Citation Graph (0, 0)][DBLP ] Conf ] Sankaran Karthik , Mark Aitken , Glidden Martin , Srinivasu Pappula , Bob Stettler , Praveen Vishakantaiah , Manuel A. d'Abreu , Jacob A. Abraham Distributed Mixed Level Logic and Fault Simulation on the Pentium® Pro Microprocessor. [Citation Graph (0, 0)][DBLP ] Conf ] Nur A. Touba , Edward J. McCluskey Altering a Pseudo-Random Bit Sequence for Scan-Based BIST. [Citation Graph (0, 0)][DBLP ] Conf ] Mohammed F. AlShaibi , Charles R. Kime MFBIST: A BIST Method for Random Pattern Resistant Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Nadime Zacharia , Janusz Rajski , Jerzy Tyszer , John A. Waicukauski Two-Dimensional Test Data Decompressor for Multiple Scan Designs. [Citation Graph (0, 0)][DBLP ] Conf ] Sybille Hellebrand , Hans-Joachim Wunderlich , Andre Hertwig Mixed-Mode BIST Using Embedded Processors. [Citation Graph (0, 0)][DBLP ] Conf ] Marly Roncken , Eric Bruls Test Quality of Asynchronous Circuits: A Defect-oriented Evaluation. [Citation Graph (0, 0)][DBLP ] Conf ] Marly Roncken , Emile H. L. Aarts , Wim F. J. Verhaegh Optimal Scan for Pipelined Testing: An Asynchronous Foundation. [Citation Graph (0, 0)][DBLP ] Conf ] Volker Schöber , Thomas Kiel An Asynchronous Scan Path Concept for Micropipelines using the Bundled Data Convention. [Citation Graph (0, 0)][DBLP ] Conf ] Montek Singh , Steven M. Nowick Synthesis-for-Initializability of Asynchronous Sequential Machines. [Citation Graph (0, 0)][DBLP ] Conf ] Timothy R. Henry , Thomas Soo Burn-in Elimination of a High Volume Microprocessor Using IDDQ . [Citation Graph (0, 0)][DBLP ] Conf ] Peter C. Maxwell , Robert C. Aitken , Kathleen R. Kollitz , Allen C. Brown IDDQ and AC Scan: The War Against Unmodelled Defects. [Citation Graph (0, 0)][DBLP ] Conf ] Alan W. Righter , Jerry M. Soden , Richard W. Beegle High Resolution IDDQ Characterization and Testing - Practical Issues. [Citation Graph (0, 0)][DBLP ] Conf ] K. Ozaki , H. Sekiguchi , S. Wakana , Y. Goto , Y. Umehara , J. Matsumoto Novel Optical Probing System with Submicron Spatial Resolution for Internal Diagnosis of VLSI Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Marwan A. Gharaybeh , Michael L. Bushnell , Vishwani D. Agrawal An Exact Non-Enumerative Fault Simulator for Path-Delay Faults. [Citation Graph (0, 0)][DBLP ] Conf ] Patrick Girard , Christian Landrault , Serge Pravossoudovitch , B. Rodriguez A Diagnostic ATPG for Delay Faults Based on Genetic Algorithms. [Citation Graph (0, 0)][DBLP ] Conf ] Ismed Hartanto , Vamsi Boppana , W. Kent Fuchs Diagnostic Fault Equivalence Identification Using Redundancy Information and Structural Analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Piero Olivo , Marcello Dalpasso Self-Learning Signature Analysis for Non-Volatile Memory Testing. [Citation Graph (0, 0)][DBLP ] Conf ] Anne Meixner , Jash Banik Weak Write Test Mode: An SRAM Cell Stability Design for Test Technique. [Citation Graph (0, 0)][DBLP ] Conf ] Narumi Sakashita , Fumihiro Okuda , Ken'ichi Shimomura , Hiroki Shimano , Mitsuhiro Hamada , Tetsuo Tada , Shinji Komori , Kazuo Kyuma , Akihiko Yasuoka , Haruhiko Abe A Built-In Self-Test Circuit with Timing Margin Test Function in a 1Gbit Synchronous DRAM. [Citation Graph (0, 0)][DBLP ] Conf ] Christophe Vaucher , Louis Balme Analog/Digital Testing of Loaded Boards Without Dedicated Test Points. [Citation Graph (0, 0)][DBLP ] Conf ] Mick Tegethoff , Kenneth P. Parker , Ken Lee Opens Board Test Coverage: When is 99% Really 40%? [Citation Graph (0, 0)][DBLP ] Conf ] D. Eugene Wedge , Tom Conner A Roadmap for Boundary-Scan Test Reuse. [Citation Graph (0, 0)][DBLP ] Conf ] Harry Hengster , Uwe Sparmann , Bernd Becker , Sudhakar M. Reddy Local Transformations and Robust Dependent Path Delay. [Citation Graph (0, 0)][DBLP ] Conf ] Irith Pomeranz , Sudhakar M. Reddy On Cancelling the Effects of Logic Sharing for Improved Path Delay Fault Testability. [Citation Graph (0, 0)][DBLP ] Conf ] Jonathan T.-Y. Chang , Edward J. McCluskey Detecting Delay Flaws by Very-Low-Voltage Testing. [Citation Graph (0, 0)][DBLP ] Conf ] F. Pichon Testability Features for a Submicron Voice-coder ASIC. [Citation Graph (0, 0)][DBLP ] Conf ] Hugo Cheung , Sandeep K. Gupta A BIST Methodology for Comprehensive Testing of RAM with Reduced Heat Dissipation. [Citation Graph (0, 0)][DBLP ] Conf ] Wayne M. Needham , Naga Gollakota DFT Strategy for Intel Microprocessors. [Citation Graph (0, 0)][DBLP ] Conf ] Lee Whetsel Proposal to Simplify Development of a Mixed-Signal Test Standard. [Citation Graph (0, 0)][DBLP ] Conf ] Robert J. Russell A Method of Extending an 1149.1 Bus for Mixed-Signal Testing. [Citation Graph (0, 0)][DBLP ] Conf ] Keith Lofstrom Early Capture for Boundary Scan Timing Measurements. [Citation Graph (0, 0)][DBLP ] Conf ] Angela Krstic , Kwang-Ting Cheng , Srimat T. Chakradhar Identification and Test Generation for Primitive Faults. [Citation Graph (0, 0)][DBLP ] Conf ] G. M. Luong , D. M. H. Walker Test Generation for Global Delay Faults. [Citation Graph (0, 0)][DBLP ] Conf ] Dimitrios Karayiannis , Spyros Tragoudas ATPD: An Automatic Test Pattern Generator for Path Delay Faults. [Citation Graph (0, 0)][DBLP ] Conf ] Yasuji Oyama , Toshinobu Kanai , Hironobu Niijima Scan Design Oriented Test Technique for VLSI's Using ATE. [Citation Graph (0, 0)][DBLP ] Conf ] Klaus Helmreich , G. Reinwardt Virtual Test of Noise and Jitter Parameters. [Citation Graph (0, 0)][DBLP ] Conf ] Yuhai Ma , Wanchun Shi A Novel Approach to the Analysis of VLSI Device Test Programs. [Citation Graph (0, 0)][DBLP ] Conf ] James F. Plusquellic , Donald M. Chiarulli , Steven P. Levitan Digital Integrated Circuit Testing using Transient Signal Analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Jos van Sas , Urbain Swerts , Marc Darquennes Towards an Effective IDDQ Test Vector Selection and Application Methodology. [Citation Graph (0, 0)][DBLP ] Conf ] Theo J. Powell , James R. Pair , Bernard G. Carbajal III Correlating Defects to Functional and IDDQ Tests. [Citation Graph (0, 0)][DBLP ] Conf ] Thomas Olbrich , Jordi Pérez , Ian A. Grout , Andrew M. D. Richardson , Carles Ferrer Defect-Oriented vs. Schematic-Level Based Fault Simulation for Mixed-Signal ICs. [Citation Graph (0, 0)][DBLP ] Conf ] Giri Devarayanadurg , Prashant Goteti , Mani Soma Hierarchy Based Statistical Fault Simulation of Mixed-Signal ICs. [Citation Graph (0, 0)][DBLP ] Conf ] Evan M. Hawrysh , Gordon W. Roberts An Integration of Memory-Based Analog Signal Generation into Current DFT Architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Vamsi Boppana , W. Kent Fuchs Partial Scan Design Based on State Transition Modeling. [Citation Graph (0, 0)][DBLP ] Conf ] Dong Xiang , Janak H. Patel A Global Algorithm for the Partial Scan Design Problem Using Circuit State Information. [Citation Graph (0, 0)][DBLP ] Conf ] Fulvio Corno , Paolo Prinetto , Maurizio Rebaudengo , Matteo Sonza Reorda Partial Scan Flip Flop Selection for Simulation-Based Sequential ATPGs. [Citation Graph (0, 0)][DBLP ] Conf ] Anthony Taylor , Gregory A. Maston Standard Test Interface Language (STIL): A New Language for Patterns and Waveforms. [Citation Graph (0, 0)][DBLP ] Conf ] Naim Ben Hamida , Khaled Saab , David Marche , Bozena Kaminska , Guy Quesnel LIMSoft: Automated Tool for Design and Test Integration of Analog Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Ilene Burnstein , Taratip Suwannasart , Robert Carlson Developing a Testing Maturity Model for Software Test Process Evaluation and Improvement. [Citation Graph (0, 0)][DBLP ] Conf ] Von-Kyoung Kim , Mick Tegethoff , Tom Chen ASIC Yield Estimation at Early Design Cycle. [Citation Graph (0, 0)][DBLP ] Conf ] Daniel P. Core Risk Assessment Sampling Plans for Non-Standard (Maverick) Material. [Citation Graph (0, 0)][DBLP ] Conf ] Jos van der Peet , Ger van Boxem SPC on the IC-Production Test Process. [Citation Graph (0, 0)][DBLP ] Conf ] David B. Lavo , Tracy Larrabee , Brian Chess Beyond the Byzantine Generals: Unexpected Behaviour and Bridging Fault Diagnosis. [Citation Graph (0, 0)][DBLP ] Conf ] F. Celeiro , L. Dias , J. Ferreira , Marcelino B. Santos , João Paulo Teixeira Defect-Oriented IC Test and Diagnosis Using VHDL Fault Simulation. [Citation Graph (0, 0)][DBLP ] Conf ] Li-C. Wang , M. Ray Mercer , Thomas W. Williams Using Target Faults To Detect Non-Tartget Defects. [Citation Graph (0, 0)][DBLP ] Conf ] Sandeep Bhatia , Tushar Gheewala , Prab Varma A Unifying Methodology for Intellectual Property and Custom Logic Testing. [Citation Graph (0, 0)][DBLP ] Conf ] Nagesh Tamarapalli , Janusz Rajski Constructive Multi-Phase Test Point Insertion for Scan-Based BIST. [Citation Graph (0, 0)][DBLP ] Conf ] Robert B. Norwood , Edward J. McCluskey Orthogonal Scan: Low-Overhead Scan for Data Paths. [Citation Graph (0, 0)][DBLP ] Conf ] Kazunori Chihara , Takashi Sekino , Koji Sasaki An Application of Photoconductive Switch for High-Speed Testing. [Citation Graph (0, 0)][DBLP ] Conf ] Hideaki Imada , Kenichi Fujisaki , Toshimi Ohsawa , Masaru Tsuto Generation Technique of 500MHz Ultra-High Speed Algorithmic Pattern. [Citation Graph (0, 0)][DBLP ] Conf ] Michael G. Davis The Effect of Periof Generation Techniques on Period Resolution and Waveform Jitter in VLSI Test Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Piero Franco , Siyad C. Ma , Jonathan Chang , Yi-Chin Chu , Sanjay Wattal , Edward J. McCluskey , Robert L. Stokes , William D. Farwell Analysis and Detection of Timing Failures in an Experimental Test Chip. [Citation Graph (0, 0)][DBLP ] Conf ] David Potts , Roger Griesmer A Unique Methodology for At-Speed Test of cDSPTM and ASIC Devices. [Citation Graph (0, 0)][DBLP ] Conf ] Ralf Stoffels Cost Effective Frequency Measurement for Production Testing. [Citation Graph (0, 0)][DBLP ] Conf ] Wuudiann Ke Backplane Interconnect Test in a Boundary-Scan Environment. [Citation Graph (0, 0)][DBLP ] Conf ] Yves Le Traon , Ghassan Al Hayek , Chantal Robach Testability-Oriented Hardware/Software Partitioning. [Citation Graph (0, 0)][DBLP ] Conf ] Pablo Sanchez , Isabel Hidalgo System Level Fault Simulation. [Citation Graph (0, 0)][DBLP ] Conf ] Tom Eberle , Robert McVay , Chris Meyers , Jason Moore ASIC BIST Synthesis: A VHDL Approach. [Citation Graph (0, 0)][DBLP ] Conf ] James Beausang , Chris Ellingham , Markus Robinson Integrating Scan into Hierarchical Synthesis Methodologies. [Citation Graph (0, 0)][DBLP ] Conf ] Vishwani D. Agrawal , Ronald D. Blanton , Maurizio Damiani Synthesis of Self-Testing Finite State Machines from High-Level Specifications. [Citation Graph (0, 0)][DBLP ] Conf ] Yuyun Liao , D. M. H. Walker Fault Coverage Analysis for Physically-Based CMOS Bridging Faults at Different Power Supply Voltages. [Citation Graph (0, 0)][DBLP ] Conf ] Michael J. Ohletz Realistic-Faults Mapping Scheme for the Fault Simulation of Integrated Analogue CMOS Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Thomas W. Williams , R. H. Dennard , Rohit Kapur , M. Ray Mercer , Wojciech Maly IDDQ Test: Sensitivity Analysis of Scaling. [Citation Graph (0, 0)][DBLP ] Conf ] Hiromu Fujioka , Koji Nakamae , Akio Higashi Effects of Multi-Product, Small-Sized Production of LSIs Packaged in Various Packages on the Final Test Process Efficiency and Cost. [Citation Graph (0, 0)][DBLP ] Conf ] Felix Frayman , Mick Tegethoff , Brenton White Issues in Optimizing the Test Process - A Telecom Case Study. [Citation Graph (0, 0)][DBLP ] Conf ] Matthew Boutin , Peter Dziel Application of Boundary Scan in a Fault Tolerant Computer System. [Citation Graph (0, 0)][DBLP ] Conf ] Koppolu Sasidhar , Abhijit Chatterjee , Yervant Zorian Optimal Multiple Chain Relay Testing Scheme for MCMs on Large Area Substrates. [Citation Graph (0, 0)][DBLP ] Conf ] Andrew Flint Three Different MCMs, Three Different Test Strategies. [Citation Graph (0, 0)][DBLP ] Conf ] Edward P. Sayre MCM Compute Node Thermal Failure - Design or Test Problem? [Citation Graph (0, 0)][DBLP ] Conf ] Carl Pixley , Noel R. Strader , W. C. Bruce , Jaehong Park , Matt Kaufmann , Kurt Shultz , Michael Burns , Jainendra Kumar , Jun Yuan , Janet Nguyen Commercial Design Verification: Methodology and Tools. [Citation Graph (0, 0)][DBLP ] Conf ] Marc E. Levitt Formal Verification of the UltraSPARCTM Family of Processors via ATPG Methods. [Citation Graph (0, 0)][DBLP ] Conf ] Neeta Ganguly , Magdy S. Abadir , Manish Pandey PowerPCTM Array Verification Methodology using Formal Techniques. [Citation Graph (0, 0)][DBLP ] Conf ] Shi-Yu Huang , Kwang-Ting Cheng , Kuang-Chien Chen , Uwe Gläser An ATPG-Based Framework for Verifying Sequential Equivalence. [Citation Graph (0, 0)][DBLP ] Conf ] Dinos Moundanos , Jacob A. Abraham , Yatin Vasant Hoskote A Unified Framework for Design Validation and Manufacturing Test. [Citation Graph (0, 0)][DBLP ] Conf ] Ghassan Al Hayek , Chantal Robach From Specification Validation to Hardware Testing: A Unified Method. [Citation Graph (0, 0)][DBLP ] Conf ] Duncan Clarke , Insup Lee Testing-Based Analysis of Real-Time System Models. [Citation Graph (0, 0)][DBLP ] Conf ] Irith Pomeranz , Nirmal R. Saxena , Richard Reeve , Paritosh Kulkarni , Yan A. Li Generation of Test Cases for Hardware Design Verification of a Super-Scalar Fetch Processor. [Citation Graph (0, 0)][DBLP ] Conf ] Melvin A. Breuer , Sandeep K. Gupta Process-Aggravated Noise (PAN): New Validation and Test Problems. [Citation Graph (0, 0)][DBLP ] Conf ] Kenneth P. Parker Introduction ITC 1996 Lecture Series on Unpowered Opens Testing. [Citation Graph (0, 0)][DBLP ] Conf ] Ted T. Turner Capacitive Leadframe Testing. [Citation Graph (0, 0)][DBLP ] Conf ] Jack Ferguson High Fault Coverage of In-Circuit IC Pin Faults with a Vectorless Test Technique Using Parasitic Transistors. [Citation Graph (0, 0)][DBLP ] Conf ] Joe Wrinn Two New Techniques for Identifying Opens on Printed Circuit Boards: Analog Junction Test, and Radio Frequency Induction Test. [Citation Graph (0, 0)][DBLP ] Conf ] Anthony J. Suto Analog AC Harmonic Method for Detecting Solder Opens. [Citation Graph (0, 0)][DBLP ] Conf ] Stig Oresjo Unpowered Opens Test with X-Ray Laminography. [Citation Graph (0, 0)][DBLP ] Conf ] David P. Vallett An Overview of CMOS VLSI Failure Analysis and the Importance of Test and Diagnostics. [Citation Graph (0, 0)][DBLP ] Conf ] Robert C. Aitken Modelling the Unmodellable: Algorithmic Fault Diagnosis. [Citation Graph (0, 0)][DBLP ] Conf ] Keith Baker , Jos van Beers Shmoo Plots - the Black Art of IC Test. [Citation Graph (0, 0)][DBLP ] Conf ] Kenneth M. Butler , Karl Johnson , Jeff Platt , Anjali Jones , Jayashree Saxena Integrating Automated Diagnosis into the Testing and Failure Analysis Operations. [Citation Graph (0, 0)][DBLP ] Conf ] Jerry M. Soden , Richard E. Anderson , Christopher L. Henderson IC Failure Analysis Tools and Techniques - Macig, Mystery, and Science. [Citation Graph (0, 0)][DBLP ] Conf ] Donald Staab Practical Issues of Failure Diagnosis and Analysis in a Fast Cycle Time Environment. [Citation Graph (0, 0)][DBLP ] Conf ] William R. Simpson The Key to Concurrent Engineering is Design Tools. [Citation Graph (0, 0)][DBLP ] Conf ] Stephen B. Furber The Return of Asynchronous Logic. [Citation Graph (0, 0)][DBLP ] Conf ] Marly Roncken Asynchronous Design: Working the Fast Lane. [Citation Graph (0, 0)][DBLP ] Conf ] Rochit Rajsuman Challenge of the 90's: Testing CoreWareTM Based ASICs. [Citation Graph (0, 0)][DBLP ] Conf ] Peter Dziel The Need for Complete System Level Test Standardization. [Citation Graph (0, 0)][DBLP ] Conf ] Manoj Sachdev Deep Sub-micron IDDQ Test Options. [Citation Graph (0, 0)][DBLP ] Conf ] 