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Martin Margala: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Sadeka Ali, Gregory Briggs, Martin Margala
    A High Frequency, Low Jitter Auto-Calibration Phase-Locked Loop with Built-in-Self-Test. [Citation Graph (0, 0)][DBLP]
    DFT, 2005, pp:591-600 [Conf]
  2. Marco S. Dragic, Martin Margala
    Power Supply Current Test Approach for Resistive Fault Screening in Embedded Analog Circuits. [Citation Graph (0, 0)][DBLP]
    DFT, 2003, pp:124-131 [Conf]
  3. Viera Stopjaková, D. Micusík, Lubica Benusková, Martin Margala
    Neural Networks-Based Parametric Testing of Analog IC. [Citation Graph (0, 0)][DBLP]
    DFT, 2002, pp:408-418 [Conf]
  4. Michael Wieckowski, John Liobe, Quentin Diduck, Martin Margala
    A New Test Methodology For DNL Error In Flash ADC's. [Citation Graph (0, 0)][DBLP]
    DFT, 2005, pp:582-590 [Conf]
  5. Dan Zhao, Shambhu J. Upadhyaya, Martin Margala
    Control Constrained Resource Partitioning for Complex SoCs. [Citation Graph (0, 0)][DBLP]
    DFT, 2003, pp:425-432 [Conf]
  6. Marco Lanuzza, Stefania Perri, Martin Margala, Pasquale Corsonello
    Low-Cost Fully Reconfigurable Data-Path for FPGA-Based Multimedia Processor. [Citation Graph (0, 0)][DBLP]
    FPL, 2005, pp:13-18 [Conf]
  7. Rong Lin, Martin Margala
    Novel design and verification of a 16 x 16-b self-repairable reconfigurable inner product processor. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2002, pp:172-177 [Conf]
  8. Dan Zhao, Shambhu J. Upadhyaya, Martin Margala
    Minimizing concurrent test time in SoC's by balancing resource usage. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2002, pp:77-82 [Conf]
  9. Brian W. Curran, Mary Gifaldi, Jason Martin, Alper Buyuktosunoglu, Martin Margala, David H. Albonesi
    Low-Voltage 0, 25 µm CMOS Improved Power Adaptive Issue Queue for Embedded Microprocessors. [Citation Graph (0, 0)][DBLP]
    VLSI-SOC, 2001, pp:289-300 [Conf]
  10. Martin Margala, Srdjan Dragic, Ahmed El-Abasiry, Samuel Ekpe, Viera Stopjaková
    I-V Fast IDDQ Current Sensor for On-Line Mixed-Signal/Analog Test. [Citation Graph (0, 0)][DBLP]
    IOLTW, 2000, pp:92-93 [Conf]
  11. Sadeka Ali, Martin Margala
    A 5.1-GHz CMOS PLL based integer-N frequency synthesizer with ripple-free control voltage and improved acquisition time. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2004, pp:237-240 [Conf]
  12. Quentin Diduck, Martin Margala
    6-bit low power low area frequency modulation based flash ADC. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2004, pp:137-140 [Conf]
  13. Natalia Kazakova, R. Sung, Nelson G. Durdle, Martin Margala, Julien Lamoureux
    Fast and low-power inner product processor. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:646-649 [Conf]
  14. Natalia Kazakova, Martin Margala, Nelson G. Durdle
    Sobel edge detection processor for a real-time volume rendering system. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2004, pp:913-916 [Conf]
  15. Srdjan Dragic, Igor M. Filanovsky, Martin Margala
    Low-voltage analog current detector supporting at-speed BIST. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2002, pp:593-596 [Conf]
  16. Marco Lanuzza, Martin Margala, Pasquale Corsonello
    Cost-effective low-power processor-in-memory-based reconfigurable datapath for multimedia applications. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2005, pp:161-166 [Conf]
  17. Karthik Sundararaman, Shambhu J. Upadhyaya, Martin Margala
    Cost Model Analysis of DFT Based Fault Tolerant SOC Designs. [Citation Graph (0, 0)][DBLP]
    ISQED, 2004, pp:465-469 [Conf]
  18. Srdjan Dragic, Martin Margala
    A 1.2V Built-In Architecture for High Frequency On-Line Iddq/delta Iddq Test. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2002, pp:165-170 [Conf]
  19. Martin Margala
    Low Power SRAMs for Battery Operation. [Citation Graph (0, 0)][DBLP]
    MTDT, 1999, pp:6-0 [Conf]
  20. Martin Margala
    Low-Power SRAM Circuit Design. [Citation Graph (0, 0)][DBLP]
    MTDT, 1999, pp:115-122 [Conf]
  21. Martin Margala, Quentin Diduck, Eric Moule
    1.8V 0.18µm CMOS Novel Successive Approximation ADC. [Citation Graph (0, 0)][DBLP]
    VLSI-SOC, 2003, pp:375-379 [Conf]
  22. Martin Margala, Magdy A. El-Moursy, Ali El-Moursy, Junmou Zhang, Wendi Beth Heinzelman
    1-V ADPCM Processor for Low-Power Wireless Applications. [Citation Graph (0, 0)][DBLP]
    VLSI-SOC, 2003, pp:386-393 [Conf]
  23. Martin Margala, John Liobe, Quentin Diduck
    Deep-Submicron CMOS Design Methodology for High-Performance Low-Power Analog-to-Digital Converters. [Citation Graph (0, 0)][DBLP]
    VLSI-SOC, 2003, pp:380-385 [Conf]
  24. Antonija Soldo, Anand Gopalan, P. R. Mukund, Martin Margala
    A Current Sensor for On-Chip, Non-Intrusive Testing of RF Systems. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2004, pp:1023-1026 [Conf]
  25. Brian Moore, Christopher J. Backhouse, Martin Margala
    Design of Wireless Sub-Micron Characterization System. [Citation Graph (0, 0)][DBLP]
    VTS, 2004, pp:341-346 [Conf]
  26. Martin Margala
    Adaptable Architectures for Signal Processing Applications. [Citation Graph (0, 0)][DBLP]
    AHS, 2006, pp:247-254 [Conf]
  27. Martin Margala, Nelson G. Durdle, Scott Juskiw, V. James Raso, Doug L. Hill
    A 33 MHz 16-bit gradient calculator for real-time volume imaging. [Citation Graph (0, 0)][DBLP]
    Computers & Graphics, 1995, v:19, n:5, pp:679-684 [Journal]
  28. Martin Margala, Hongfan Wang
    New approach to design for reusability of arithmetic cores in systems-on-chip. [Citation Graph (0, 0)][DBLP]
    Integration, 2004, v:38, n:2, pp:185-203 [Journal]
  29. Dan Zhao, Shambhu J. Upadhyaya, Martin Margala
    Design of a wireless test control network with radio-on-chip technology for nanometer system-on-a-chip. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:7, pp:1411-1418 [Journal]
  30. Brian Moore, Martin Margala, Christopher J. Backhouse
    Design of wireless on-wafer submicron characterization system. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:2, pp:169-180 [Journal]
  31. Anand Gopalan, Martin Margala, P. R. Mukund
    A current based self-test methodology for RF front-end circuits. [Citation Graph (0, 0)][DBLP]
    Microelectronics Journal, 2005, v:36, n:12, pp:1091-1102 [Journal]
  32. John Liobe, Martin Margala
    Novel Process and Temperature-Stable BICS for Embedded Analog and Mixed-Signal Test. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2007, pp:231-236 [Conf]
  33. Sandeep Patil, Michael Wieckowski, Martin Margala
    A Self-Biased Charge-Transfer Sense Amplifier. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3030-3033 [Conf]
  34. Richard Geisler, John Liobe, Martin Margala
    Process and Temperature Calibration of PLLs with BiST Capabilities. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3864-3867 [Conf]
  35. Yunan Xiang, R. Pettibon, Martin Margala
    A versatile computation module for adaptable multimedia processors. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  36. Quentin Diduck, John Liobe, Sadeka Ali, Martin Margala
    Process tolerant calibration circuit for PLL applications with BIST. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  37. Pasquale Corsonello, Stefania Perri, Martin Margala
    An integrated countermeasure against differential power analysis for secure smart-cards. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  38. Yuxin Wang, Martin Margala
    New Embedded Core Testing for System-on-Chips and System-in-Packages. [Citation Graph (0, 0)][DBLP]
    CCECE, 2006, pp:1897-1900 [Conf]
  39. Yuxin Wang, D. Makadia, Martin Margala
    On-Chip Integrated Antennas - The First Challenge for Reliable on-Chip Wireless Interconnects. [Citation Graph (0, 0)][DBLP]
    CCECE, 2006, pp:2322-2325 [Conf]
  40. Viera Stopjaková, P. Malosek, M. Matej, Vladislav Nagy, Martin Margala
    Defect detection in analog and mixed circuits by neural networks using wavelet analysis. [Citation Graph (0, 0)][DBLP]
    IEEE Transactions on Reliability, 2005, v:54, n:3, pp:441-448 [Journal]
  41. Brandon J. Jasionowski, Michelle K. Lay, Martin Margala
    A Processor-In-Memory Architecture for Multimedia Compression. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:4, pp:478-483 [Journal]

  42. A Digital BIST for Phase-Locked Loops. [Citation Graph (, )][DBLP]

  43. Programming Model and Low-level Language for a Coarse-Grained Reconfigurable Multimedia Processor. [Citation Graph (, )][DBLP]

  44. A low cost reconfigurable soft processor for multimedia applications: Design synthesis and programming model. [Citation Graph (, )][DBLP]

  45. New performance/power/area efficient, reliable full adder design. [Citation Graph (, )][DBLP]

  46. Varicap threshold logic. [Citation Graph (, )][DBLP]

  47. A 1.2v, 1.02 ghz 8 bit SIMD compatible highly parallel arithmetic data path for multi-precision arithmetic. [Citation Graph (, )][DBLP]

  48. Study of leakage current mechanisms in ballistic deflection transistors. [Citation Graph (, )][DBLP]

  49. Design of self correcting radiation hardened digital circuits using decoupled ground bus. [Citation Graph (, )][DBLP]

  50. Topology impact on the room temperature performance of THz-range ballistic deflection transistors. [Citation Graph (, )][DBLP]

  51. A portless SRAM Cell using stunted wordline drivers. [Citation Graph (, )][DBLP]

  52. Energy Efficient Coarse-Grain Reconfigurable Array for Accelerating Digital Signal Processing. [Citation Graph (, )][DBLP]

  53. Design-Space Exploration of Energy-Delay-Area Efficient Coarse-Grain Reconfigurable Datapath. [Citation Graph (, )][DBLP]

  54. A New Reconfigurable Coarse-Grain Architecture for Multimedia Applications. [Citation Graph (, )][DBLP]

  55. A new built-in IDDQ testing method using programmable BICS. [Citation Graph (, )][DBLP]

  56. Power/throughput/area efficient PIM-based reconfigurable array for parallel processing. [Citation Graph (, )][DBLP]

  57. Power-Efficient High Throughput Reconfigurable Datapath Design for Portable Multimedia Devices. [Citation Graph (, )][DBLP]

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