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Xiaoqing Wen :
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Yasumi Doi , Seiji Kajihara , Xiaoqing Wen , Lei Li , Krishnendu Chakrabarty Test compression for scan circuits using scan polarity adjustment and pinpoint test relaxation. [Citation Graph (0, 0)][DBLP ] ASP-DAC, 2005, pp:59-64 [Conf ] Masayasu Fukunaga , Seiji Kajihara , Xiaoqing Wen , Toshiyuki Maeda , Shuji Hamada , Yasuo Sato A dynamic test compaction procedure for high-quality path delay testing. [Citation Graph (0, 0)][DBLP ] ASP-DAC, 2006, pp:348-353 [Conf ] Xiaoqing Wen Fault Diagnosis for Static CMOS Circuits. [Citation Graph (0, 0)][DBLP ] Asian Test Symposium, 1997, pp:282-287 [Conf ] Kohei Miyase , Kenta Terashima , Seiji Kajihara , Xiaoqing Wen , Sudhakar M. Reddy On Improving Defect Coverage of Stuck-at Fault Tests. [Citation Graph (0, 0)][DBLP ] Asian Test Symposium, 2005, pp:216-223 [Conf ] Xiaoqing Wen , Tooru Honzawa , Hideo Tamamoto , Kewal K. Saluja , Kozo Kinoshita Design for Diagnosability of CMOS Circuits. [Citation Graph (0, 0)][DBLP ] Asian Test Symposium, 1998, pp:144-149 [Conf ] Xiaoqing Wen , Hideo Tamamoto , Kozo Kinoshita Transistor leakage fault location with ZDDQ measurement. [Citation Graph (0, 0)][DBLP ] Asian Test Symposium, 1995, pp:51-57 [Conf ] Xiaoqing Wen , Hideo Tamamoto , Kewal K. Saluja , Kozo Kinoshita Fault Diagnosis for Physical Defects of Unknown Behaviors. [Citation Graph (0, 0)][DBLP ] Asian Test Symposium, 2003, pp:236-241 [Conf ] Xiaoqing Wen , Hsin-Po Wang A Flexible Logic BIST Scheme and Its Application to SoC Designs. [Citation Graph (0, 0)][DBLP ] Asian Test Symposium, 2001, pp:463- [Conf ] Hiroshi Yokoyama , Xiaoqing Wen , Hideo Tamamoto Random Pattern Testable Design with Partial Circuit Duplication. [Citation Graph (0, 0)][DBLP ] Asian Test Symposium, 1997, pp:353-358 [Conf ] Seiji Kajihara , Masayasu Fukunaga , Xiaoqing Wen , Toshiyuki Maeda , Shuji Hamada , Yasuo Sato Path delay test compaction with process variation tolerance. [Citation Graph (0, 0)][DBLP ] DAC, 2005, pp:845-850 [Conf ] B. Cheon , E. Lee , Laung-Terng Wang , Xiaoqing Wen , P. Hsu , J. Cho , J. Park , H. Chao , Shianling Wu At-Speed Logic BIST for IP Cores. [Citation Graph (0, 0)][DBLP ] DATE, 2005, pp:860-861 [Conf ] Xiaoqing Wen , Tokiharu Miyoshi , Seiji Kajihara , Laung-Terng Wang , Kewal K. Saluja , Kozo Kinoshita On per-test fault diagnosis using the X-fault model. [Citation Graph (0, 0)][DBLP ] ICCAD, 2004, pp:633-640 [Conf ] Xiaoqing Wen , Kewal K. Saluja A new method towards achieving global optimality in technology mapping. [Citation Graph (0, 0)][DBLP ] ICCAD, 1996, pp:9-12 [Conf ] Laung-Terng Wang , Xiaoqing Wen , Po-Ching Hsu , Shianling Wu , Jonhson Guo At-Speed Logic BIST Architecture for Multi-Clock Designs. [Citation Graph (0, 0)][DBLP ] ICCD, 2005, pp:475-478 [Conf ] Laung-Terng Wang , Khader S. Abdel-Hafez , Shianling Wu , Xiaoqing Wen , Hiroshi Furukawa , Fei-Sheng Hsu , Shyh-Horng Lin , Sen-Wei Tsai VirtualScan: A New Compressed Scan Technology for Test Cost Reduction. [Citation Graph (0, 0)][DBLP ] ITC, 2004, pp:916-925 [Conf ] Xiaoqing Wen , Kozo Kinoshita Testable Designs of Sequential Circuits Under Highly Observable Condition. [Citation Graph (0, 0)][DBLP ] ITC, 1992, pp:632-641 [Conf ] Yu Hu , Xiaowei Li , Huawei Li , Xiao-Qing Wen Compression/Scan Co-Design for Reducing Test Data Volume, Scan-in Power Dissipation and Test Application Time. [Citation Graph (0, 0)][DBLP ] PRDC, 2005, pp:175-182 [Conf ] Xiaoqing Wen , Seiji Kajihara , Kohei Miyase , Tatsuya Suzuki , Kewal K. Saluja , Laung-Terng Wang , Khader S. Abdel-Hafez , Kozo Kinoshita A New ATPG Method for Efficient Capture Power Reduction During Scan Testing. [Citation Graph (0, 0)][DBLP ] VTS, 2006, pp:58-65 [Conf ] Xiaoqing Wen , Yoshiyuki Yamashita , Seiji Kajihara , Laung-Terng Wang , Kewal K. Saluja , Kozo Kinoshita On Low-Capture-Power Test Generation for Scan Testing. [Citation Graph (0, 0)][DBLP ] VTS, 2005, pp:265-270 [Conf ] Xiaoqing Wen , Hideo Tamamoto , Kewal K. Saluja , Kozo Kinoshita Fault Diagnosis of Physical Defects Using Unknown Behavior Model. [Citation Graph (0, 0)][DBLP ] J. Comput. Sci. Technol., 2005, v:20, n:2, pp:187-194 [Journal ] Xiaoqing Wen , Hideo Tamamoto , Kozo Kinoshita IDDQ test vector selection for transistor short fault testing. [Citation Graph (0, 0)][DBLP ] Systems and Computers in Japan, 1997, v:28, n:5, pp:11-21 [Journal ] Hiroshi Yokoyama , Xiaoqing Wen , Hideo Tamamoto Random pattern testable design with partial circuit duplication and IDDQ testing. [Citation Graph (0, 0)][DBLP ] Systems and Computers in Japan, 1999, v:30, n:5, pp:18-27 [Journal ] Xiaoqing Wen , Kozo Kinoshita A Testable Design of Logic Circuits under Highly Observable Condition. [Citation Graph (0, 0)][DBLP ] IEEE Trans. Computers, 1992, v:41, n:5, pp:654-659 [Journal ] Xiaoqing Wen , Kohei Miyase , Tatsuya Suzuki , Seiji Kajihara , Yuji Ohsumi , Kewal K. Saluja Critical-Path-Aware X-Filling for Effective IR-Drop Reduction in At-Speed Scan Testing. [Citation Graph (0, 0)][DBLP ] DAC, 2007, pp:527-532 [Conf ] Nicola Nicolici , Xiaoqing Wen Embedded Tutorial on Low Power Test. [Citation Graph (0, 0)][DBLP ] European Test Symposium, 2007, pp:202-210 [Conf ] B. Cheon , E. Lee , Laung-Terng Wang , Xiaoqing Wen , P. Hsu , J. Cho , J. Park , H. Chao , Shianling Wu At-Speed Logic BIST for IP Cores [Citation Graph (0, 0)][DBLP ] CoRR, 2007, v:0, n:, pp:- [Journal ] Xiaoqing Wen , Tatsuya Suzuki , Seiji Kajihara , Kohei Miyase , Yoshihiro Minamoto , Laung-Terng Wang , Kewal K. Saluja Efficient Test Set Modification for Capture Power Reduction. [Citation Graph (0, 0)][DBLP ] J. Low Power Electronics, 2005, v:1, n:3, pp:319-330 [Journal ] CAT: A Critical-Area-Targeted Test Set Modification Scheme for Reducing Launch Switching Activity in At-Speed Scan Testing. [Citation Graph (, )][DBLP ] Power-Aware Testing and Test Strategies for Low Power Devices. [Citation Graph (, )][DBLP ] Test Strategies for Low Power Devices. [Citation Graph (, )][DBLP ] Diagnosis of Realistic Defects Based on the X-Fault Model. [Citation Graph (, )][DBLP ] On Optimizing Fault Coverage, Pattern Count, and ATPG Run Time Using a Hybrid Single-Capture Scheme for Testing Scan Designs. [Citation Graph (, )][DBLP ] Estimation of delay test quality and its application to test generation. [Citation Graph (, )][DBLP ] Effective IR-drop reduction in at-speed scan testing using Distribution-Controlling X-Identification. [Citation Graph (, )][DBLP ] A novel post-ATPG IR-drop reduction scheme for at-speed scan testing in broadcast-scan-based test compression environment. [Citation Graph (, )][DBLP ] Highly-Guided X-Filling Method for Effective Low-Capture-Power Scan Test Generation. [Citation Graph (, )][DBLP ] A GA-Based Method for High-Quality X-Filling to Reduce Launch Switching Activity in At-speed Scan Testing. [Citation Graph (, )][DBLP ] On estimation of NBTI-Induced delay degradation. [Citation Graph (, )][DBLP ] VirtualScan: Test Compression Technology Using Combinational Logic and One-Pass ATPG. [Citation Graph (, )][DBLP ] Turbo1500: Core-Based Design for Test and Diagnosis. [Citation Graph (, )][DBLP ] Search in 0.002secs, Finished in 0.003secs