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Wolfgang Nebel: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Frank Oppenheimer, Dongming Zhang, Wolfgang Nebel
    Modelling Communication Interfaces with COMIX. [Citation Graph (0, 0)][DBLP]
    Ada-Europe, 2001, pp:337-348 [Conf]
  2. Guido Schumacher, Wolfgang Nebel
    How to Avoid the Inheritance Anomaly in Ada. [Citation Graph (0, 0)][DBLP]
    Ada-Europe, 1998, pp:53-64 [Conf]
  3. Alberto Allara, Massimo Bombana, Patrizia Cavalloro, Wolfgang Nebel, Wolfram Putzke-Röming, Martin Radetzki
    ATM Cell Modelling using Objective VHDL. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1998, pp:261-264 [Conf]
  4. Wolfgang Nebel
    Predictable design of low power systems by pre-implementation estimation and optimization. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:12-17 [Conf]
  5. Jan M. Rabaey, Dennis Sylvester, David Blaauw, Kerry Bernstein, Jerry Frenkil, Mark Horowitz, Wolfgang Nebel, Takayasu Sakurai, Andrew Yang
    Reshaping EDA for power. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:15- [Conf]
  6. Gerd Jochens, Lars Kruse, Eike Schmidt, Wolfgang Nebel
    A New Parameterizable Power Macro-Model for Datapath Components. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:29-0 [Conf]
  7. Lars Kruse, Eike Schmidt, Gerd Jochens, Ansgar Stammermann, Wolfgang Nebel
    Lower Bounds on the Power Consumption in Scheduled Data Flow Graphs with Resource Constraints. [Citation Graph (0, 0)][DBLP]
    DATE, 2000, pp:737- [Conf]
  8. Eduard Moser, Wolfgang Nebel
    Case Study: System Model of Crane and Embedded Control. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:721-0 [Conf]
  9. Wolfram Putzke-Röming, Martin Radetzki, Wolfgang Nebel
    A Flexible Message Passing Mechanism for Objective VHDL. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:242-249 [Conf]
  10. Dirk Rabe, Gerd Jochens, Lars Kruse, Wolfgang Nebel, Carl von Ossietzky
    Power-Simulation of Cell Based ASICs: Accuracy- and Performance Trade-Offs. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:356-361 [Conf]
  11. Martin Radetzki, Ansgar Stammermann, Wolfram Putzke-Röming, Wolfgang Nebel
    Data Type Analysis for Hardware Synthesis from Object-Oriented Models. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:491-0 [Conf]
  12. Eike Schmidt, Gerd Jochens, Lars Kruse, Frans Theeuwen, Wolfgang Nebel
    Automatic nonlinear memory power modelling. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:808- [Conf]
  13. Thorsten Schubert, Jürgen Hanisch, Joachim Gerlach, Jens-E. Appell, Wolfgang Nebel
    Evaluation of a Refinement-Driven SystemC'-Based Design Flow. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:262-267 [Conf]
  14. Guido Schumacher, Wolfgang Nebel
    Object-Oriented Modelling of Parallel Hardware Systems. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:234-241 [Conf]
  15. Wolfgang Nebel
    System-Level Power Optimization. [Citation Graph (0, 0)][DBLP]
    DSD, 2004, pp:27-34 [Conf]
  16. Alexander Schwarz, Bärbel Mertsching, M. Brucke, Wolfgang Nebel, Jürgen Tchorz, Birger Kollmeier
    Implementing a Quantitative Model for the "Effective" Signal Processing in the Auditory System on a Dedicated Digital VLSI Hardware. [Citation Graph (0, 0)][DBLP]
    EUROMICRO, 1999, pp:1133-1139 [Conf]
  17. M. Brucke, Arne Schulz, Wolfgang Nebel
    Auditory Signal Processing in Hardware: A Linear Gammatone Filterbank Design for a Model of the Auditory System. [Citation Graph (0, 0)][DBLP]
    FPL, 1999, pp:11-20 [Conf]
  18. M. Çakir, Eike Grimpe, Wolfgang Nebel
    HW-Driven Emulation with Automatic Interface Generation. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:627-637 [Conf]
  19. Karsten Albers, Carsten Beth, Sven Frimont, Nicole Kaczoreck, Wolfgang Nebel, Andreas Schallenberg, Frank Slomka
    Smart Systems: Explorierende Roboter in der Lehre. [Citation Graph (0, 0)][DBLP]
    GI Jahrestagung (1), 2005, pp:173-177 [Conf]
  20. Kim Grüttner, Carsten Beth, Wolfgang Nebel
    Kommunikationsgetriebene Hardware-/Software Partitionierung eines Netzwerkprotokoll-Stacks auf einer SoC Plattform. [Citation Graph (0, 0)][DBLP]
    GI Jahrestagung (1), 2005, pp:324-328 [Conf]
  21. Frank Oppenheimer, Michael Kersten, Wolfgang Nebel
    OOCOSIM - Eine objekt-orientierte Co-Designmethode für eingebettete Systeme. [Citation Graph (0, 0)][DBLP]
    GI Jahrestagung (2), 2005, pp:683-687 [Conf]
  22. Arne Schulz, Wolfgang Nebel
    Verlustleistungsabschätzung und -optimierung auf hohen Abstraktionsebenen: Modellierung von Funktionskomponenten und Leitungslängenabschätzung. [Citation Graph (0, 0)][DBLP]
    GI Jahrestagung (1), 2005, pp:454- [Conf]
  23. Ansgar Stammermann, Domenik Helms, Milan Schulte, Arne Schulz, Wolfgang Nebel
    Binding, Allocation and Floorplanning in Low Power High-Level Synthesis. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2003, pp:544-550 [Conf]
  24. Michael Kersten, Wolfgang Nebel
    On Detecting Deadlocks in Large UML Models. [Citation Graph (0, 0)][DBLP]
    DIPES, 2004, pp:11-20 [Conf]
  25. Lars Kruse, Eike Schmidt, Gerd Jochens, Wolfgang Nebel
    Lower and upper bounds on the switching activity in scheduled data flow graphs. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1999, pp:115-120 [Conf]
  26. Dirk Rabe, Wolfgang Nebel
    Short circuit power consumption of glitches. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1996, pp:125-128 [Conf]
  27. Axel Reimer, Arne Schulz, Wolfgang Nebel
    Modelling macromodules for high-level dynamic power estimation of FPGA-based digital designs. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2006, pp:151-154 [Conf]
  28. Domenik Helms, Günter Ehmen, Wolfgang Nebel
    Analysis and modeling of subthreshold leakage of RT-components under PTV and state variation. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2006, pp:220-225 [Conf]
  29. Lars Kruse, Eike Schmidt, Gerd Jochens, Ansgar Stammermann, Wolfgang Nebel
    Lower Bound Estimation for Low Power High-Level Synthesis. [Citation Graph (0, 0)][DBLP]
    ISSS, 2000, pp:180-186 [Conf]
  30. Ansgar Stammermann, Lars Kruse, Wolfgang Nebel, Alexander Pratsch, Eike Schmidt, Milan Schulte, Arne Schulz
    System level optimization and design space exploration for low power. [Citation Graph (0, 0)][DBLP]
    ISSS, 2001, pp:142-146 [Conf]
  31. Domenik Helms, Eike Schmidt, Arne Schulz, Ansgar Stammermann, Wolfgang Nebel
    An Improved Power Macro-Model for Arithmetic Datapath Components. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2002, pp:16-24 [Conf]
  32. Domenik Helms, Marko Hoyer, Wolfgang Nebel
    Accurate PTV, State, and ABB Aware RTL Blackbox Modeling of Subthreshold, Gate, and PN-Junction Leakage. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2006, pp:56-65 [Conf]
  33. Domenik Helms, Eike Schmidt, Wolfgang Nebel
    Leakage in CMOS Circuits - An Introduction. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2004, pp:17-35 [Conf]
  34. Gerd Jochens, Lars Kruse, Eike Schmidt, Ansgar Stammermann, Wolfgang Nebel
    Power Macro-Modelling for Firm-Macro. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2000, pp:24-35 [Conf]
  35. Wolfgang Nebel, Bärbel Mertsching, Birger Kollmeier
    Digital Hearing Aids: Challenges and Solutions for Ultra Low Power. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2005, pp:733- [Conf]
  36. Arne Schulz, Wolfgang Nebel
    Optimization of Digital Audio Processing Algorithms Suitable for Hearing Aids. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2005, pp:735-736 [Conf]
  37. Arne Schulz, Andreas Schallenberg, Domenik Helms, Milan Schulte, Axel Reimer, Wolfgang Nebel
    A High Level Constant Coefficient Multiplier Power Model for Power Estimation on High Levels of Abstraction. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2005, pp:146-155 [Conf]
  38. Ansgar Stammermann, Domenik Helms, Milan Schulte, Arne Schulz, Wolfgang Nebel
    Interconnect Driven Low Power High-Level Synthesis. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2003, pp:131-140 [Conf]
  39. Laila Kabous, Wolfgang Nebel
    Modeling Hard Real Time Systems with UML. [Citation Graph (0, 0)][DBLP]
    UML, 1999, pp:339-355 [Conf]
  40. Giulio Gorla, Eduard Moser, Wolfgang Nebel, Eugenio Villar
    System Specification Experiments on a Common Benchmark. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2000, v:17, n:3, pp:22-32 [Journal]
  41. Hans-Jürgen Appelrath, Werner Damm, K.-H. Menke, Wolfgang Nebel, Wilfried Thoben
    OFFIS - Acht Jahre anwendungsorientierte Informatik-Forschung und -Entwicklung. [Citation Graph (0, 0)][DBLP]
    Inform., Forsch. Entwickl., 2000, v:15, n:1, pp:51-61 [Journal]
  42. Martin Radetzki, Wolfram Putzke-Röming, Wolfgang Nebel
    A Unified Approach to Object-Oriented VHDL. [Citation Graph (0, 0)][DBLP]
    J. Inf. Sci. Eng., 1998, v:14, n:3, pp:523-545 [Journal]
  43. Gila Kamhi, Sarah Miller, Stephen Bailey Mentor, Wolfgang H. Nebel, Y. C. Wong, Juergen Karmann, Enrico Macii, Stephen V. Kosonocky, Steve Curtis
    Early Power-Aware Design & Validation: Myth or Reality? [Citation Graph (0, 0)][DBLP]
    DAC, 2007, pp:210-211 [Conf]
  44. Andreas Schallenberg, Wolfgang Nebel, Frank Oppenheimer
    OSSS+R: Modelling and Simulating Self-Reconfigurable Systems. [Citation Graph (0, 0)][DBLP]
    FPL, 2006, pp:1-6 [Conf]
  45. Marko Hoyer, Domenik Helms, Wolfgang Nebel
    Modelling the Impact of High Level Leakage Optimization Techniques on the Delay of RT-Components. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2007, pp:171-180 [Conf]
  46. Sven Rosinger, Domenik Helms, Wolfgang Nebel
    RTL Power Modeling and Estimation of Sleep Transistor Based Power Gating. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2007, pp:278-287 [Conf]
  47. Florian Dittmann, Franz-Josef Rammig, M. Streubühr, Christian Haubelt, Andreas Schallenberg, Wolfgang Nebel
    Exploration, Partitioning and Simulation of Reconfigurable Systems (Exploration, Partitionierung und Simulation rekonfigurierbarer Systeme). [Citation Graph (0, 0)][DBLP]
    it - Information Technology, 2007, v:49, n:3, pp:149-0 [Journal]
  48. Lars Kruse, Eike Schmidt, Gerd Jochens, Ansgar Stammermann, Arne Schulz, E. Macii, Wolfgang Nebel
    Estimation of lower and upper bounds on the power consumption from scheduled data flow graphs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2001, v:9, n:1, pp:3-14 [Journal]
  49. Eike Schmidt, Gerd von Cölln, Lars Kruse, Frans Theeuwen, Wolfgang Nebel
    Memory power models for multilevel power estimation and optimization. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2002, v:10, n:2, pp:106-109 [Journal]

  50. On the Verification of High-Order Constraint Compliance in IC Design. [Citation Graph (, )][DBLP]


  51. SystemC-based Modelling, Seamless Refinement, and Synthesis of a JPEG 2000 Decoder. [Citation Graph (, )][DBLP]


  52. Qalitative and Quantitative Analysis of IC Designs. [Citation Graph (, )][DBLP]


  53. OSSS+R: A framework for application level modelling and synthesis of reconfigurable systems. [Citation Graph (, )][DBLP]


  54. An automated flow for integrating hardware IP into the automotive systems engineering process. [Citation Graph (, )][DBLP]


  55. Power Management Aware Low Leakage Behavioural Synthesis. [Citation Graph (, )][DBLP]


  56. Inheritance concept for signals in object-oriented extensions to VHDL. [Citation Graph (, )][DBLP]


  57. The ANDRES Project: Analysis and Design of Run-Time Reconfigurable, Heterogeneous Systems. [Citation Graph (, )][DBLP]


  58. Seamless design flow for reconfigurable systems. [Citation Graph (, )][DBLP]


  59. Green-IT - Opportunities and Challenges. [Citation Graph (, )][DBLP]


  60. High-level estimation and trade-off analysis for adaptive real-time systems. [Citation Graph (, )][DBLP]


  61. On leakage currents: sources and reduction for transistors, gates, memories and digital systems. [Citation Graph (, )][DBLP]


  62. Voltage- and ABB-island optimization in high level synthesis. [Citation Graph (, )][DBLP]


  63. Hybrid logical-statistical simulation with thermal and IR-drop mapping for degradation and variation prediction. [Citation Graph (, )][DBLP]


  64. Automatic Transformation of System Models in Automotive Electronics. [Citation Graph (, )][DBLP]


  65. Efficient Modelling and Simulation of Embedded Software Multi-Tasking using SystemC and OSSS. [Citation Graph (, )][DBLP]


  66. Using SystemC for an Extended MATLAB/Simulink Verification Flow. [Citation Graph (, )][DBLP]


  67. Connecting SystemC-AMS Models with OSCI TLM 2.0 Models using Temporal Decoupling. [Citation Graph (, )][DBLP]


  68. Modelling Program-State Machines in SystemC. [Citation Graph (, )][DBLP]


  69. CSP with Synthesisable SystemC(tm) and OSSS. [Citation Graph (, )][DBLP]


  70. The Quiny SystemC Front End: Self-Synthesising Designs. [Citation Graph (, )][DBLP]


  71. Designing for dynamic partially reconfigurable FPGAs with SystemC and OSSS. [Citation Graph (, )][DBLP]


  72. Statistical static capacity management in virtualized data centers supporting fine grained QoS specification. [Citation Graph (, )][DBLP]


  73. Power and cost aware distributed load management. [Citation Graph (, )][DBLP]


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