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Kaustav Banerjee: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Kaustav Banerjee, Sheng-Chih Lin, Navin Srivastava
    Electrothermal engineering in the nanometer era: from devices and interconnects to circuits and systems. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:223-230 [Conf]
  2. Shashidhar Mysore, Banit Agrawal, Navin Srivastava, Sheng-Chih Lin, Kaustav Banerjee, Timothy Sherwood
    Introspective 3D chips. [Citation Graph (0, 0)][DBLP]
    ASPLOS, 2006, pp:264-273 [Conf]
  3. Amir H. Ajami, Kaustav Banerjee, Massoud Pedram, Lukas P. P. P. van Ginneken
    Analysis of Non-Uniform Temperature-Dependent Interconnect Performance in High Performance ICs. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:567-572 [Conf]
  4. Kaustav Banerjee, Amit Mehrotra
    Analysis of On-Chip Inductance Effects using a Novel Performance Optimization Methodology for Distributed RLC Interconnects. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:798-803 [Conf]
  5. Kaustav Banerjee, Amit Mehrotra, Alberto L. Sangiovanni-Vincentelli, Chenming Hu
    On Thermal Effects in Deep Sub-Micron VLSI Interconnects. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:885-891 [Conf]
  6. Kaustav Banerjee, Navin Srivastava
    Are carbon nanotubes the future of VLSI interconnections? [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:809-814 [Conf]
  7. Anirban Basu, Sheng-Chih Lin, Vineet Wason, Amit Mehrotra, Kaustav Banerjee
    Simultaneous optimization of supply and threshold voltages for low-power and high-performance circuits in the leakage dominant era. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:884-887 [Conf]
  8. Hamed F. Dadgour, Rajiv V. Joshi, Kaustav Banerjee
    A novel variation-aware low-power keeper architecture for wide fan-in dynamic gates. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:977-982 [Conf]
  9. Adrian M. Ionescu, Michel J. Declercq, Santanu Mahapatra, Kaustav Banerjee, Jacques Gautier
    Few electron devices: towards hybrid CMOS-SET integrated circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:88-93 [Conf]
  10. Gian Luca Loi, Banit Agrawal, Navin Srivastava, Sheng-Chih Lin, Timothy Sherwood, Kaustav Banerjee
    A thermally-aware performance analysis of vertically integrated (3-D) processor-memory hierarchy. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:991-996 [Conf]
  11. Shukri J. Souri, Kaustav Banerjee, Amit Mehrotra, Krishna Saraswat
    Multiple Si layer ICs: motivation, performance analysis, and design implications. [Citation Graph (0, 0)][DBLP]
    DAC, 2000, pp:213-220 [Conf]
  12. Kaustav Banerjee, Amit Mehrotra
    Coupled Analysis of Electromigration Reliability and Performance in ULSI Signal Nets. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:158-164 [Conf]
  13. Amir H. Ajami, Kaustav Banerjee, Massoud Pedram
    Analysis of Substrate Thermal Gradient Effects on Optimal Buffer Insertion. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:44-48 [Conf]
  14. TingYen Chiang, Kaustav Banerjee, Krishna Saraswat
    Compact Modeling and SPICE-Based Simulation for Electrothermal Analysis of Multilevel ULSI Interconnects. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:165-0 [Conf]
  15. Adil Koukab, Kaustav Banerjee, Michel J. Declercq
    Analysis and optimization of substrate noise coupling in single-chip RF transceiver design. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2002, pp:309-316 [Conf]
  16. Santanu Mahapatra, Kaustav Banerjee, Florent Pegeon, Adrian M. Ionescu
    A CAD Framework for Co-Design and Analysis of CMOS-SET Hybrid Integrated Circuits. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2003, pp:497-503 [Conf]
  17. Navin Srivastava, Kaustav Banerjee
    Performance analysis of carbon nanotube interconnects for VLSI applications. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2005, pp:383-390 [Conf]
  18. Sheng-Chih Lin, Kaustav Banerjee
    An electrothermally-aware full-chip substrate temperature gradient evaluation methodology for leakage dominant technologies with implications for power estimation and hot-spot management. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2006, pp:568-574 [Conf]
  19. Sheng-Chih Lin, Navin Srivastava, Kaustav Banerjee
    A Thermally-Aware Methodology for Design-Specific Optimization of Supply and Threshold Voltages in Nanometer Scale ICs. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:411-416 [Conf]
  20. Santanu Mahapatra, Adrian M. Ionescu, Kaustav Banerjee, Michel J. Declercq
    A SET quantizer circuit aiming at digital communication system. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:860-863 [Conf]
  21. Vineet Wason, Kaustav Banerjee
    A probabilistic framework for power-optimal repeater insertion in global interconnects under parameter variations. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2005, pp:131-136 [Conf]
  22. Songqing Zhang, Vineet Wason, Kaustav Banerjee
    A probabilistic framework to estimate full-chips subthreshold leakage power distribution considering within-die and die-to-die P-T-V variations. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2004, pp:156-161 [Conf]
  23. Kaustav Banerjee, Massoud Pedram, Amir H. Ajami
    Analysis and optimization of thermal issues in high-performance VLSI. [Citation Graph (0, 0)][DBLP]
    ISPD, 2001, pp:230-237 [Conf]
  24. Kaustav Banerjee, Amit Mehrotra
    Inductance Aware Interconnect Scaling. [Citation Graph (0, 0)][DBLP]
    ISQED, 2002, pp:43-47 [Conf]
  25. Anirban Basu, Sheng-Chih Lin, Christoph Wasshuber, Adrian M. Ionescu, Kaustav Banerjee
    A Comprehensive Analytical Capacitance Model of a Two Dimensional Nanodot Array. [Citation Graph (0, 0)][DBLP]
    ISQED, 2004, pp:259-264 [Conf]
  26. Adrian M. Ionescu, V. Pott, R. Fritschi, Kaustav Banerjee, Michel J. Declercq, P. Renaud, C. Hibert, Philippe Flückiger, G. A. Racine
    Modeling and Design of a Low-Voltage SOI Suspended-Gate MOSFET (SG-MOSFET) with a Metal-over-Gate Architecture. [Citation Graph (0, 0)][DBLP]
    ISQED, 2002, pp:496-501 [Conf]
  27. Choshu Ito, Kaustav Banerjee, Robert W. Dutton
    Analysis and Design of ESD Protection Circuits for High-Frequency/RF Applications. [Citation Graph (0, 0)][DBLP]
    ISQED, 2001, pp:117-122 [Conf]
  28. Rajiv V. Joshi, Kaustav Banerjee, André DeHon
    Tutorial 1: Emerging Technologies for VLSI Design. [Citation Graph (0, 0)][DBLP]
    ISQED, 2006, pp:4- [Conf]
  29. Lech Józwiak, Kaustav Banerjee
    Plenary Session 2P. [Citation Graph (0, 0)][DBLP]
    ISQED, 2005, pp:461- [Conf]
  30. Man Lung Mui, Kaustav Banerjee, Amit Mehrotra
    Power Supply Optimization in sub-130 nm Leakage Dominant Technologies . [Citation Graph (0, 0)][DBLP]
    ISQED, 2004, pp:409-414 [Conf]
  31. Navin Srivastava, Xiaoning Qi, Kaustav Banerjee
    Impact of On-chip Inductance on Power Distribution Network Design for Nanometer Scale Integrated Circuits. [Citation Graph (0, 0)][DBLP]
    ISQED, 2005, pp:346-351 [Conf]
  32. Krishna Saraswat, Shukri J. Souri, Kaustav Banerjee, Pawan Kapur
    Performance analysis and technology of 3-D ICs. [Citation Graph (0, 0)][DBLP]
    SLIP, 2000, pp:85-90 [Conf]
  33. Nikil Dutt, Kaustav Banerjee, Luca Benini, Kanishka Lahiri, Sudeep Pasricha
    Tutorial 5: SoC Communication Architectures: Technology, Current Practice, Research, and Trends. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2007, pp:8- [Conf]
  34. Amir H. Ajami, Kaustav Banerjee, Massoud Pedram
    Modeling and analysis of nonuniform substrate temperature effects on global ULSI interconnects. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:6, pp:849-861 [Journal]
  35. Kaustav Banerjee, Amit Mehrotra
    Analysis of on-chip inductance effects for distributed RLC interconnects. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:8, pp:904-915 [Journal]
  36. Adil Koukab, Kaustav Banerjee, Michel J. Declercq
    Modeling techniques and verification methodologies for substrate coupling effects in mixed-signal system-on-chip designs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:6, pp:823-836 [Journal]
  37. Man Lung Mui, Kaustav Banerjee, Amit Mehrotra
    Supply and power optimization in leakage-dominant technologies. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:9, pp:1362-1371 [Journal]
  38. Hamed F. Dadgour, Kaustav Banerjee
    Design and Analysis of Hybrid NEMS-CMOS Circuits for Ultra Low-Power Applications. [Citation Graph (0, 0)][DBLP]
    DAC, 2007, pp:306-311 [Conf]
  39. Shashidhar Mysore, Banit Agrawal, Navin Srivastava, Sheng-Chih Lin, Kaustav Banerjee, Timothy Sherwood
    3D Integration for Introspection. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2007, v:27, n:1, pp:77-83 [Journal]

  40. High-speed low-power FinFET based domino logic. [Citation Graph (, )][DBLP]

  41. Analysis and implications of parasitic and screening effects on the high-frequency/RF performance of tunneling-carbon nanotube FETs. [Citation Graph (, )][DBLP]

  42. Design and analysis of compact ultra energy-efficient logic gates using laterally-actuated double-electrode NEMS. [Citation Graph (, )][DBLP]

  43. High-Frequency Mutual Impedance Extraction of VLSI Interconnects In the Presence of a Multi-layer Conducting Substrate. [Citation Graph (, )][DBLP]

  44. Efficient 3D high-frequency impedance extraction for general interconnects and inductors above a layered substrate. [Citation Graph (, )][DBLP]

  45. Aging-resilient design of pipelined architectures using novel detection and correction circuits. [Citation Graph (, )][DBLP]

  46. CMOS vs Nano: comrades or rivals? [Citation Graph (, )][DBLP]

  47. Statistical modeling of metal-gate work-function variability in emerging device technologies and implications for circuit design. [Citation Graph (, )][DBLP]

  48. Variability analysis of FinFET-based devices and circuits considering electrical confinement and width quantization. [Citation Graph (, )][DBLP]

  49. Fast 3-D thermal analysis of complex interconnect structures using electrical modeling and simulation methodologies. [Citation Graph (, )][DBLP]

  50. A new paradigm in the design of energy-efficient digital circuits using laterally-actuated double-gate NEMs. [Citation Graph (, )][DBLP]

  51. Graphene based transistors: physics, status and future perspectives. [Citation Graph (, )][DBLP]

  52. Graphene based nanomaterials for VLSI interconnect and energy-storage applications. [Citation Graph (, )][DBLP]

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