Sheng-Chih Lin, Kaustav Banerjee An electrothermally-aware full-chip substrate temperature gradient evaluation methodology for leakage dominant technologies with implications for power estimation and hot-spot management. [Citation Graph (0, 0)][DBLP] ICCAD, 2006, pp:568-574 [Conf]
Vineet Wason, Kaustav Banerjee A probabilistic framework for power-optimal repeater insertion in global interconnects under parameter variations. [Citation Graph (0, 0)][DBLP] ISLPED, 2005, pp:131-136 [Conf]
Kaustav Banerjee, Amit Mehrotra Analysis of on-chip inductance effects for distributed RLC interconnects. [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:8, pp:904-915 [Journal]
Adil Koukab, Kaustav Banerjee, Michel J. Declercq Modeling techniques and verification methodologies for substrate coupling effects in mixed-signal system-on-chip designs. [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:6, pp:823-836 [Journal]
High-speed low-power FinFET based domino logic. [Citation Graph (, )][DBLP]
Analysis and implications of parasitic and screening effects on the high-frequency/RF performance of tunneling-carbon nanotube FETs. [Citation Graph (, )][DBLP]
Design and analysis of compact ultra energy-efficient logic gates using laterally-actuated double-electrode NEMS. [Citation Graph (, )][DBLP]
High-Frequency Mutual Impedance Extraction of VLSI Interconnects In the Presence of a Multi-layer Conducting Substrate. [Citation Graph (, )][DBLP]
Efficient 3D high-frequency impedance extraction for general interconnects and inductors above a layered substrate. [Citation Graph (, )][DBLP]
Aging-resilient design of pipelined architectures using novel detection and correction circuits. [Citation Graph (, )][DBLP]
Statistical modeling of metal-gate work-function variability in emerging device technologies and implications for circuit design. [Citation Graph (, )][DBLP]
Variability analysis of FinFET-based devices and circuits considering electrical confinement and width quantization. [Citation Graph (, )][DBLP]
Fast 3-D thermal analysis of complex interconnect structures using electrical modeling and simulation methodologies. [Citation Graph (, )][DBLP]
A new paradigm in the design of energy-efficient digital circuits using laterally-actuated double-gate NEMs. [Citation Graph (, )][DBLP]
Graphene based transistors: physics, status and future perspectives. [Citation Graph (, )][DBLP]
Graphene based nanomaterials for VLSI interconnect and energy-storage applications. [Citation Graph (, )][DBLP]
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