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Gurindar S. Sohi: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Philip M. Wells, Koushik Chakraborty, Gurindar S. Sohi
    Hardware support for spin management in overcommitted virtual machines. [Citation Graph (0, 0)][DBLP]
    PACT, 2006, pp:124-133 [Conf]
  2. J. Adam Butts, Gurindar S. Sohi
    Dynamic dead-instruction detection and elimination. [Citation Graph (0, 0)][DBLP]
    ASPLOS, 2002, pp:199-210 [Conf]
  3. Jaehyuk Huh, Jichuan Chang, Doug Burger, Gurindar S. Sohi
    Coherence decoupling: making use of incoherence. [Citation Graph (0, 0)][DBLP]
    ASPLOS, 2004, pp:97-106 [Conf]
  4. Avinash Sodani, Gurindar S. Sohi
    An Empirical Analysis of Instruction Repetition. [Citation Graph (0, 0)][DBLP]
    ASPLOS, 1998, pp:35-45 [Conf]
  5. Gurindar S. Sohi, Manoj Franklin
    High-Bandwidth Data Memory Systems for Superscalar Processors. [Citation Graph (0, 0)][DBLP]
    ASPLOS, 1991, pp:53-62 [Conf]
  6. Gurindar S. Sohi, Sriram Vajapeyam
    Tradeoffs in Instruction Format Design for Horizontal Architectures. [Citation Graph (0, 0)][DBLP]
    ASPLOS, 1989, pp:15-25 [Conf]
  7. Amir Roth, Andreas Moshovos, Gurindar S. Sohi
    Dependance Based Prefetching for Linked Data Structures. [Citation Graph (0, 0)][DBLP]
    ASPLOS, 1998, pp:115-126 [Conf]
  8. Koushik Chakraborty, Philip M. Wells, Gurindar S. Sohi
    Computation spreading: employing hardware migration to specialize CMP cores on-the-fly. [Citation Graph (0, 0)][DBLP]
    ASPLOS, 2006, pp:283-292 [Conf]
  9. Andrew R. Pleszkun, Gurindar S. Sohi, Bassam Z. Kahhaleh, Edward S. Davidson
    Features of the Structured Memory Access (SMA) Architecture. [Citation Graph (0, 0)][DBLP]
    COMPCON, 1986, pp:259-265 [Conf]
  10. Gurindar S. Sohi
    Microprocessors - 10 Years Back, 10 Years Ahead. [Citation Graph (0, 0)][DBLP]
    Informatics, 2001, pp:209-218 [Conf]
  11. Gurindar S. Sohi
    Amir Roth: Speculative Multithreaded Processors. [Citation Graph (0, 0)][DBLP]
    HiPC, 2000, pp:259-270 [Conf]
  12. Sridhar Gopal, T. N. Vijaykumar, James E. Smith, Gurindar S. Sohi
    Speculative Versioning Cache. [Citation Graph (0, 0)][DBLP]
    HPCA, 1998, pp:195-205 [Conf]
  13. Amir Roth, Gurindar S. Sohi
    Speculative Data-Driven Multithreading. [Citation Graph (0, 0)][DBLP]
    HPCA, 2001, pp:37-0 [Conf]
  14. Andreas Moshovos, Gurindar S. Sohi
    Memory Dependence Speculation Tradeoffs in Centralized, Continuous-Window Superscalar Processors. [Citation Graph (0, 0)][DBLP]
    HPCA, 2000, pp:301-312 [Conf]
  15. Craig B. Zilles, Gurindar S. Sohi
    A Programmable Co-Processor for Profiling. [Citation Graph (0, 0)][DBLP]
    HPCA, 2001, pp:241-0 [Conf]
  16. Paramjit S. Oberoi, Gurindar S. Sohi
    Out-of-Order Instruction Fetch Using Multiple Sequencers. [Citation Graph (0, 0)][DBLP]
    ICPP, 2002, pp:14-0 [Conf]
  17. Amir Roth, Andreas Moshovos, Gurindar S. Sohi
    Improving virtual function call target prediction via dependence-based pre-computation. [Citation Graph (0, 0)][DBLP]
    International Conference on Supercomputing, 1999, pp:356-364 [Conf]
  18. Gurindar S. Sohi, James E. Smith, James R. Goodman
    Restricted Fetch&Phi operations for parallel processing. [Citation Graph (0, 0)][DBLP]
    ICS, 1989, pp:410-416 [Conf]
  19. Saisanthosh Balakrishnan, Gurindar S. Sohi
    Program Demultiplexing: Data-flow based Speculative Parallelization of Methods in Sequential Programs. [Citation Graph (0, 0)][DBLP]
    ISCA, 2006, pp:302-313 [Conf]
  20. Todd M. Austin, Dionisios N. Pnevmatikatos, Gurindar S. Sohi
    Streamlining Data Cache Access with Fast Address Calculation. [Citation Graph (0, 0)][DBLP]
    ISCA, 1995, pp:369-380 [Conf]
  21. Todd M. Austin, Gurindar S. Sohi
    Dynamic Dependency Analysis of Ordinary Programs. [Citation Graph (0, 0)][DBLP]
    ISCA, 1992, pp:342-351 [Conf]
  22. Todd M. Austin, Gurindar S. Sohi
    High-Bandwidth Address Translation for Multiple-Issue Processors. [Citation Graph (0, 0)][DBLP]
    ISCA, 1996, pp:158-167 [Conf]
  23. J. Adam Butts, Gurindar S. Sohi
    Use-Based Register Caching with Decoupled Indexing. [Citation Graph (0, 0)][DBLP]
    ISCA, 2004, pp:302-313 [Conf]
  24. Jichuan Chang, Gurindar S. Sohi
    Cooperative Caching for Chip Multiprocessors. [Citation Graph (0, 0)][DBLP]
    ISCA, 2006, pp:264-276 [Conf]
  25. Kifung C. Cheung, Gurindar S. Sohi, Kewal K. Saluja, Dhiraj K. Pradhan
    Organization and Analysis of a Gracefully-Degrading Interleaved Memory System. [Citation Graph (0, 0)][DBLP]
    ISCA, 1987, pp:224-231 [Conf]
  26. Manoj Franklin, Gurindar S. Sohi
    The Expandable Split Window Paradigm for Exploiting Fine-Grain Parallelism. [Citation Graph (0, 0)][DBLP]
    ISCA, 1992, pp:58-67 [Conf]
  27. Paramjit S. Oberoi, Gurindar S. Sohi
    Parallelism in the Front-End. [Citation Graph (0, 0)][DBLP]
    ISCA, 2003, pp:230-240 [Conf]
  28. Andreas Moshovos, Scott E. Breach, T. N. Vijaykumar, Gurindar S. Sohi
    Dynamic Speculation and Synchronization of Data Dependences. [Citation Graph (0, 0)][DBLP]
    ISCA, 1997, pp:181-193 [Conf]
  29. Andrew R. Pleszkun, Gurindar S. Sohi
    The Performance Potential of Multiple Functional Unit Processors. [Citation Graph (0, 0)][DBLP]
    ISCA, 1988, pp:37-44 [Conf]
  30. Dionisios N. Pnevmatikatos, Gurindar S. Sohi
    Guarded Executing and Branch Prediction in Dynamic ILP Processors. [Citation Graph (0, 0)][DBLP]
    ISCA, 1994, pp:120-129 [Conf]
  31. Amir Roth, Gurindar S. Sohi
    Effective Jump-Pointer Prefetching for Linked Data Structures. [Citation Graph (0, 0)][DBLP]
    ISCA, 1999, pp:111-121 [Conf]
  32. Steven L. Scott, Gurindar S. Sohi
    Using Feedback to Control Tree Saturation in Multistage Interconnection Networks. [Citation Graph (0, 0)][DBLP]
    ISCA, 1989, pp:167-176 [Conf]
  33. Avinash Sodani, Gurindar S. Sohi
    Dynamic Instruction Reuse. [Citation Graph (0, 0)][DBLP]
    ISCA, 1997, pp:194-205 [Conf]
  34. Gurindar S. Sohi
    Retrospective: Instruction Issue Logic for High-Performance, Interruptable Pipelined Processors. [Citation Graph (0, 0)][DBLP]
    25 Years ISCA: Retrospectives and Reprints, 1998, pp:51-53 [Conf]
  35. Gurindar S. Sohi
    Retrospective: Multiscalar Processors. [Citation Graph (0, 0)][DBLP]
    25 Years ISCA: Retrospectives and Reprints, 1998, pp:111-114 [Conf]
  36. Gurindar S. Sohi, Scott E. Breach, T. N. Vijaykumar
    Multiscalar Processors. [Citation Graph (0, 0)][DBLP]
    ISCA, 1995, pp:414-425 [Conf]
  37. Gurindar S. Sohi, Scott E. Breach, T. N. Vijaykumar
    Multiscalar Processors. [Citation Graph (0, 0)][DBLP]
    25 Years ISCA: Retrospectives and Reprints, 1998, pp:521-532 [Conf]
  38. Gurindar S. Sohi, Edward S. Davidson, Janak H. Patel
    An Efficient LISP-Execution Architecture with a New Representation for List Structures. [Citation Graph (0, 0)][DBLP]
    ISCA, 1985, pp:91-98 [Conf]
  39. Gurindar S. Sohi, Sriram Vajapeyam
    Instruction Issue Logic for High-Performance, Interruptable Pipelined Processors. [Citation Graph (0, 0)][DBLP]
    ISCA, 1987, pp:27-34 [Conf]
  40. Gurindar S. Sohi, Sriram Vajapeyam
    Instruction Issue Logic for High-Performance, Interruptable Pipelined Processors. [Citation Graph (0, 0)][DBLP]
    25 Years ISCA: Retrospectives and Reprints, 1998, pp:329-336 [Conf]
  41. Sriram Vajapeyam, Gurindar S. Sohi, Wei-Chung Hsu
    An Empirical Study of the CRAY Y-MP Processor Using the Perfect Club Benchmarks. [Citation Graph (0, 0)][DBLP]
    ISCA, 1991, pp:170-179 [Conf]
  42. Craig B. Zilles, Gurindar S. Sohi
    Understanding the backward slices of performance degrading instructions. [Citation Graph (0, 0)][DBLP]
    ISCA, 2000, pp:172-181 [Conf]
  43. Craig B. Zilles, Gurindar S. Sohi
    Execution-based prediction using speculative slices. [Citation Graph (0, 0)][DBLP]
    ISCA, 2001, pp:2-13 [Conf]
  44. Scott E. Breach, T. N. Vijaykumar, Gurindar S. Sohi
    The anatomy of the register file in a multiscalar processor. [Citation Graph (0, 0)][DBLP]
    MICRO, 1994, pp:181-190 [Conf]
  45. J. Adam Butts, Gurindar S. Sohi
    A static power model for architects. [Citation Graph (0, 0)][DBLP]
    MICRO, 2000, pp:191-201 [Conf]
  46. J. Adam Butts, Gurindar S. Sohi
    Characterizing and predicting value degree of use. [Citation Graph (0, 0)][DBLP]
    MICRO, 2002, pp:15-26 [Conf]
  47. Todd M. Austin, Gurindar S. Sohi
    Zero-cycle loads: microarchitecture support for reducing load latency. [Citation Graph (0, 0)][DBLP]
    MICRO, 1995, pp:82-92 [Conf]
  48. Saisanthosh Balakrishnan, Gurindar S. Sohi
    Exploiting Value Locality in Physical Register Files. [Citation Graph (0, 0)][DBLP]
    MICRO, 2003, pp:265-276 [Conf]
  49. Manoj Franklin, Gurindar S. Sohi
    Register traffic analysis for streamlining inter-operation communication in fine-grain parallel processors. [Citation Graph (0, 0)][DBLP]
    MICRO, 1992, pp:236-245 [Conf]
  50. Andreas Moshovos, Gurindar S. Sohi
    Streamlining Inter-Operation Memory Communication via Data Dependence Prediction. [Citation Graph (0, 0)][DBLP]
    MICRO, 1997, pp:235-245 [Conf]
  51. Andreas Moshovos, Gurindar S. Sohi
    Read-After-Read Memory Dependence Prediction. [Citation Graph (0, 0)][DBLP]
    MICRO, 1999, pp:177-185 [Conf]
  52. Andrew R. Pleszkun, Gurindar S. Sohi
    Multiple instruction issue and single-chip processors. [Citation Graph (0, 0)][DBLP]
    MICRO, 1988, pp:64-66 [Conf]
  53. Dionisios N. Pnevmatikatos, Manoj Franklin, Gurindar S. Sohi
    Control flow prediction for dynamic ILP processors. [Citation Graph (0, 0)][DBLP]
    MICRO, 1993, pp:153-163 [Conf]
  54. Amir Roth, Gurindar S. Sohi
    Register integration: a simple and efficient implementation of squash reuse. [Citation Graph (0, 0)][DBLP]
    MICRO, 2000, pp:223-234 [Conf]
  55. Amir Roth, Gurindar S. Sohi
    A quantitative framework for automated pre-execution thread selection. [Citation Graph (0, 0)][DBLP]
    MICRO, 2002, pp:430-441 [Conf]
  56. Avinash Sodani, Gurindar S. Sohi
    Understanding the Differences Between Value Prediction and Instruction Reuse. [Citation Graph (0, 0)][DBLP]
    MICRO, 1998, pp:205-215 [Conf]
  57. Gurindar S. Sohi
    Single-Chip Multiprocessors: The Next Wave of Computer Architecture Innovation. [Citation Graph (0, 0)][DBLP]
    MICRO, 2004, pp:143- [Conf]
  58. T. N. Vijaykumar, Gurindar S. Sohi
    Task Selection for a Multiscalar Processor. [Citation Graph (0, 0)][DBLP]
    MICRO, 1998, pp:81-92 [Conf]
  59. Craig B. Zilles, Joel S. Emer, Gurindar S. Sohi
    The Use of Multithreading for Exception Handling. [Citation Graph (0, 0)][DBLP]
    MICRO, 1999, pp:219-229 [Conf]
  60. Craig B. Zilles, Gurindar S. Sohi
    Master/slave speculative parallelization. [Citation Graph (0, 0)][DBLP]
    MICRO, 2002, pp:85-96 [Conf]
  61. Todd M. Austin, Scott E. Breach, Gurindar S. Sohi
    Efficient Detection of All Pointer and Array Access Errors. [Citation Graph (0, 0)][DBLP]
    PLDI, 1994, pp:290-301 [Conf]
  62. MenChow Chiang, Gurindar S. Sohi
    Experience with Mean Value Analysis Models for Evaluating Shared Bus, Throughput-Oriented Multiprocessors. [Citation Graph (0, 0)][DBLP]
    SIGMETRICS, 1991, pp:90-100 [Conf]
  63. V. S. Madan, C.-J. Peng, Gurindar S. Sohi
    On the Adequacy of Direct Mapped Caches for Lisp and Prolog Data Reference Patterns. [Citation Graph (0, 0)][DBLP]
    NACLP, 1989, pp:888-906 [Conf]
  64. Gurindar S. Sohi, Amir Roth
    Speculative Multithreaded Processors. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 2001, v:34, n:4, pp:66-71 [Journal]
  65. Shreekant S. Thakkar, Michel Dubois, Anthony T. Laundrie, Gurindar S. Sohi, David V. James, Stein Gjessing, Manu Thapar, Bruce Delagi, Michael J. Carlton, Alvin M. Despain
    Scalable Shared-Memory Multiprocessor Architectures. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 1990, v:23, n:6, pp:71-83 [Journal]
  66. Andreas Moshovos, Gurindar S. Sohi
    Speculative Memory Cloaking and Bypassing. [Citation Graph (0, 0)][DBLP]
    International Journal of Parallel Programming, 1999, v:27, n:6, pp:427-456 [Journal]
  67. Andreas Moshovos, Gurindar S. Sohi
    Memory Dependence Prediction in Multimedia Applications. [Citation Graph (0, 0)][DBLP]
    J. Instruction-Level Parallelism, 2000, v:2, n:, pp:- [Journal]
  68. Amir Roth, Gurindar S. Sohi
    Squash Reuse via a Simplified Implementation of Register Integration. [Citation Graph (0, 0)][DBLP]
    J. Instruction-Level Parallelism, 2001, v:3, n:, pp:- [Journal]
  69. T. N. Vijaykumar, Gurindar S. Sohi
    Task Selection for the Multiscalar Architecture. [Citation Graph (0, 0)][DBLP]
    J. Parallel Distrib. Comput., 1999, v:58, n:2, pp:132-158 [Journal]
  70. Jaehyuk Huh, Doug Burger, Jichuan Chang, Gurindar S. Sohi
    Speculative Incoherent Cache Protocols. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2004, v:24, n:6, pp:104-109 [Journal]
  71. Mary K. Vernon, Rajeev Jog, Gurindar S. Sohi
    Performance Analysis of Hierarchical Cache-Consistent Multiprocessors. [Citation Graph (0, 0)][DBLP]
    Perform. Eval., 1989, v:9, n:4, pp:287-302 [Journal]
  72. MenChow Chiang, Gurindar S. Sohi
    Evaluating Design Choices for Shared Bus Multiprocessors in a Throughput-Oriented Environment. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1992, v:41, n:3, pp:297-317 [Journal]
  73. Kifung C. Cheung, Gurindar S. Sohi, Kewal K. Saluja, Dhiraj K. Pradhan
    Design and Analysis of a Gracefully Degrading Interleaved Memory System. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1990, v:39, n:1, pp:63-71 [Journal]
  74. Manoj Franklin, Gurindar S. Sohi
    ARB: A Hardware Mechanism for Dynamic Reordering of Memory References. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1996, v:45, n:5, pp:552-571 [Journal]
  75. Andreas Moshovos, Gurindar S. Sohi
    Reducing Memory Latency via Read-after-Read Memory Dependence Prediction. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2002, v:51, n:3, pp:313-326 [Journal]
  76. Gurindar S. Sohi
    Cache Memory Organization to Enhance the Yield of High-Performance VLSI Processors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1989, v:38, n:4, pp:484-492 [Journal]
  77. Gurindar S. Sohi
    Instruction Issue Logic for High-Performance Interruptible, Multiple Functional Unit, Pipelines Computers. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1990, v:39, n:3, pp:349-359 [Journal]
  78. Gurindar S. Sohi
    High-Bandwidth Interleaved Memories for Vector Processors-A Simulation Study. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1993, v:42, n:1, pp:34-44 [Journal]
  79. Alvin R. Lebeck, Gurindar S. Sohi
    Request Combining in Multiprocessors with Arbitrary Interconnection Networks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 1994, v:5, n:11, pp:1140-1155 [Journal]
  80. Steven L. Scott, Gurindar S. Sohi
    The Use of Feedback in Multiprocessors and Its Application to Tree Saturation Control. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 1990, v:1, n:4, pp:385-398 [Journal]
  81. T. N. Vijaykumar, Sridhar Gopal, James E. Smith, Gurindar S. Sohi
    Speculative Versioning Cache. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 2001, v:12, n:12, pp:1305-1317 [Journal]
  82. Jichuan Chang, Gurindar S. Sohi
    Cooperative cache partitioning for chip multiprocessors. [Citation Graph (0, 0)][DBLP]
    ICS, 2007, pp:242-252 [Conf]

  83. Adapting to Intermittent Faults in Future Multicore Systems. [Citation Graph (, )][DBLP]


  84. Adapting to intermittent faults in multicore systems. [Citation Graph (, )][DBLP]


  85. Mixed-mode multicore reliability. [Citation Graph (, )][DBLP]


  86. Serializing instructions in system-intensive workloads: Amdahl's Law strikes again. [Citation Graph (, )][DBLP]


  87. Serialization sets: a dynamic dependence-based parallel execution model. [Citation Graph (, )][DBLP]


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