Conferences in DBLP
Edward B. Eichelberger Experiences and Expectations in VLSI Testing. [Citation Graph (0, 0)][DBLP ] Conf ] Paul M. Russo The Growth of Application Specific Integrated Circuits: Opportunities and Challenges. [Citation Graph (0, 0)][DBLP ] Conf ] Thomas M. McWilliams Easing the Transition from Design to Test. [Citation Graph (0, 0)][DBLP ] Conf ] John Manzo Complexity, Test, and the Productivity Challenge of the 90s. [Citation Graph (0, 0)][DBLP ] Conf ] John Stone , Howard Ignatius , Randall Nuss Parallel Programming Significantly Improves Production NVM Wafer Sort. [Citation Graph (0, 0)][DBLP ] Conf ] Peter Nystrom , Steven Cosgrove Power Conditioning Provides Documented Productivity Gains in Semiconductor Fabrication and ATE. [Citation Graph (0, 0)][DBLP ] Conf ] Judith E. Dayhoff , Robert W. Atherton Financial Implications of a Detailed Analysis of Test Floor Operations. [Citation Graph (0, 0)][DBLP ] Conf ] Ken Lindsay Low Cost Test System Speeds Design Verification for Custom VLSI. [Citation Graph (0, 0)][DBLP ] Conf ] Matthew Adiletta , Elizabeth M. Cooper , Keith Gutfreund Automatic Test Generation for Generic Scan Designs. [Citation Graph (0, 0)][DBLP ] Conf ] Miron Abramovici , James J. Kulikowski , Premachandran R. Menon , David T. Miller Test Generation In Lamp2: System Overview. [Citation Graph (0, 0)][DBLP ] Conf ] Miron Abramovici , James J. Kulikowski , Premachandran R. Menon , David T. Miller Test Generation In Lamp2: Concepts and Algorithms. [Citation Graph (0, 0)][DBLP ] Conf ] Sivanarayana Mallela , Shianling Wu A Sequential Circuit Test Generation System. [Citation Graph (0, 0)][DBLP ] Conf ] Angelo C. Hung , Francis C. Wang A Method for Test Generation Directly from Testability Analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Erwin Trischler Guided Inconsistent Path Sensitization: Method And Experimental Results. [Citation Graph (0, 0)][DBLP ] Conf ] Dilip K. Bhavsar "Concatenable Polydividers": Bit-Sliced LFSR Chips for Board Self-Test. [Citation Graph (0, 0)][DBLP ] Conf ] Cary K. Chin , Edward J. McCluskey Test Length for Pseudo Random Testing. [Citation Graph (0, 0)][DBLP ] Conf ] Jacob Savir , William H. McAnney , Salvatore R. Vecchio Random Pattern Testing for Data-Line Faults in an Embedded Multiport Memory. [Citation Graph (0, 0)][DBLP ] Conf ] Jacob Savir , William H. McAnney , Salvatore R. Vecchio Random Pattern Testing for Address-Line Faults in an Embedded Multiport Memory. [Citation Graph (0, 0)][DBLP ] Conf ] John Salick , Bill Underwood , M. Ray Mercer Built-In Self Test Input Generator for Programmable Logic Arrays. [Citation Graph (0, 0)][DBLP ] Conf ] Gary L. Craig , Charles R. Kime Pseudo-Exhaustive Adjacency Testing: A BIST Approach for Stuck-Open Faults. [Citation Graph (0, 0)][DBLP ] Conf ] Sherri Klosterman A Computer System Diagnostic Strategy Based on ROM-Resident Diagnostics. [Citation Graph (0, 0)][DBLP ] Conf ] Aamer Mahmood , Edward J. McCluskey , Aydin Ersoz Concurrent System-Level Error Detection Using a Watchdog Processor. [Citation Graph (0, 0)][DBLP ] Conf ] David S. Curry Semiconductor Test Equipment Viewed as an Auto-Alignment System. [Citation Graph (0, 0)][DBLP ] Conf ] Donald H. Lenhert The Uses and Costs of the Addition of Remote Operation Capability to New Products. [Citation Graph (0, 0)][DBLP ] Conf ] David M. Jacobson A Fast, Probabilistic Algorithm for Functional Testing of Random Access Memory Systems. [Citation Graph (0, 0)][DBLP ] Conf ] William Corley , David S. Curry RF Calibration in ATE Systems. [Citation Graph (0, 0)][DBLP ] Conf ] David C. Chu Calibration of Systematic Errors in Precision Time-Interval Counters. [Citation Graph (0, 0)][DBLP ] Conf ] Jim Healy , Gary Ure A Method of Reducing ATE System Error Components and Guaranteeing Subnanosecond Measurement Accuracies. [Citation Graph (0, 0)][DBLP ] Conf ] Dennis Petrich Achieving Accurate Timing Measurements on TTL/CMOS Devices in a Manufacturing/Incoming Inspection Environment. [Citation Graph (0, 0)][DBLP ] Conf ] Garry C. Gillette Timing Accuracy Measurement System. [Citation Graph (0, 0)][DBLP ] Conf ] Robert J. Feugate Jr. , Steven M. McIntyre Training Tomorrow's Test Engineers: Experiences in Teaching an Undergraduate Course in VLSI Testing. [Citation Graph (0, 0)][DBLP ] Conf ] Albert B. Grubbs Jr. , Glenn Neland Future Trends in Test of Electronic Circuits With Implications tor Entry Level Test Professionals. [Citation Graph (0, 0)][DBLP ] Conf ] Edward J. McCluskey Test Teaching. [Citation Graph (0, 0)][DBLP ] Conf ] Alexander Miczo What Do You Say When Writing a Text About Test ? [Citation Graph (0, 0)][DBLP ] Conf ] Kenneth Rose Test Technology In a University Setting. [Citation Graph (0, 0)][DBLP ] Conf ] Al A. Tuszynski Curriculum for a Rapidly Changing Technology. [Citation Graph (0, 0)][DBLP ] Conf ] James G. Wilber Enhancing Device Test Programming Productivity: The CATalyst Automated Test Program Generator. [Citation Graph (0, 0)][DBLP ] Conf ] Keiji Muranaga , Kyoshiro Sakurada , Yukio Oikawa Language Independent Test Generation. [Citation Graph (0, 0)][DBLP ] Conf ] Shmuel Shalem DIP : A Diagnostics Processor. [Citation Graph (0, 0)][DBLP ] Conf ] Maurizio Contini The Autopal Test Process. [Citation Graph (0, 0)][DBLP ] Conf ] Claude J. Pany Simplifying Analog Device Test Program Generation. [Citation Graph (0, 0)][DBLP ] Conf ] Tom Middleton Recycling Functional Test Vectors: Techniques and Tools for Pattern Conversion. [Citation Graph (0, 0)][DBLP ] Conf ] Harry H. Chen , Robert G. Mathews , John A. Newkirk An Algorithm to Generate Tests for MOS Circuits at the Switch Level. [Citation Graph (0, 0)][DBLP ] Conf ] R. Chandramouli , Hector R. Sucar Defect Analysis and Fault Modeling in MOS Technology. [Citation Graph (0, 0)][DBLP ] Conf ] Mark E. Turner , Duane G. Leet , Ronald J. Prilik , David J. McLean Testing CMOS VLSI: Tools, Concepts, and Experimental Results. [Citation Graph (0, 0)][DBLP ] Conf ] T. Shimono , K. Oozeki , M. Takahashi , Masato Kawai , S. Funatsu An AC/DC Test Generation System for Gate Array LSIs. [Citation Graph (0, 0)][DBLP ] Conf ] Kenneth D. Wagner The Error Latency of Delay Faults in Combinational and Sequential Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Gordon L. Smith Model for Delay Faults Based upon Paths. [Citation Graph (0, 0)][DBLP ] Conf ] Paul H. Bardell , William H. McAnney Self-Test of Random Access Memories. [Citation Graph (0, 0)][DBLP ] Conf ] Robert H. Fujii , Jacob A. Abraham Self-Test for Microprocessors. [Citation Graph (0, 0)][DBLP ] Conf ] Andrzej Krasniewski , Alexander Albicki Automatic Design of Exhaustively Self-Testing Chips with Bilbo Modules. [Citation Graph (0, 0)][DBLP ] Conf ] Frances D. Koo , Gene W. Lee Isolating Failures within VLSI Chips That Incorporate Signature Analysis and Set/Scan Techniques. [Citation Graph (0, 0)][DBLP ] Conf ] Frans P. M. Beenker Systematic and Structured Methods for Digital Board Testing. [Citation Graph (0, 0)][DBLP ] Conf ] Stephen F. Filippone Automating Test-Bed Fault Detection and Diagnosis. [Citation Graph (0, 0)][DBLP ] Conf ] Jaffery C. Phillips A Programmable Bus Emulation Technique for Processor Based and Peripheral Printed Circuit Boards. [Citation Graph (0, 0)][DBLP ] Conf ] Dom Marro Automatic Visual Test of Surface Mount Assemblies. [Citation Graph (0, 0)][DBLP ] Conf ] Scott T. Jones Flexible Inspection Systems (FIS) for Printed Circuit Board Production: ATE Finds a Quality Partner. [Citation Graph (0, 0)][DBLP ] Conf ] Herb Boulton New Concepts of Applying Thermographic Testing to Printed Circuit Boards and Finished Products. [Citation Graph (0, 0)][DBLP ] Conf ] Antony K. Stevens MHz Frequency Counting with VLSI Testers 420. [Citation Graph (0, 0)][DBLP ] Conf ] D. R. Morris Universal Signal Routing Card. [Citation Graph (0, 0)][DBLP ] Conf ] Ryozou Yoshino , Ryuichi Takagi Custom VLSI Test System. [Citation Graph (0, 0)][DBLP ] Conf ] M. Shimizu , N. Okino , J. Nishiura , H. Maruyama Memory Embedded VLSI Gate Array Testing. [Citation Graph (0, 0)][DBLP ] Conf ] D. Rodgers , M. Shepherd Asynchronous FIFO's Require Special Attention. [Citation Graph (0, 0)][DBLP ] Conf ] Hiroshi Miyamoto , Koichiro Mashiko , Yoshikazu Morooka , Kazutami Arimoto , Michihiro Yamada , T. Nakano Test Pattern Considerations for Fault Tolerant High Density DRAM. [Citation Graph (0, 0)][DBLP ] Conf ] T. Fujieda , N. Arai Considerations of the Testing of RAMs with Dual Ports. [Citation Graph (0, 0)][DBLP ] Conf ] T. Sridhar A New Parallel Test Approach for Large Memories. [Citation Graph (0, 0)][DBLP ] Conf ] Grady Giles , Craig Hunter A Methodology for Testing Content Addressable Memories. [Citation Graph (0, 0)][DBLP ] Conf ] Nagesh Vasanthavada , Peter N. Marinos An Operationally Efficient Scheme for Exhaustive Test-Pattern Generation Using Linear Codes. [Citation Graph (0, 0)][DBLP ] Conf ] Magdy S. Abadir , Hassan K. Reghbati Functional Test Generation for LSI Circuits Described by Binary Decision Diagrams. [Citation Graph (0, 0)][DBLP ] Conf ] Wu-Tung Cheng , Janak H. Patel Multiple-Fault Detection in Iterative Logic Arrays. [Citation Graph (0, 0)][DBLP ] Conf ] Vinod K. Agarwal , Janusz Rajski Testing Properties and Applications of Inverter-Free PLA's. [Citation Graph (0, 0)][DBLP ] Conf ] Andrew V. Goldberg , Karl J. Lieberherr Efficient Test Generation Algorithms. [Citation Graph (0, 0)][DBLP ] Conf ] Jill M. McPhee The Effects of Backdriving Integrated Circuits : An Accurate Electro-Thermal Model. [Citation Graph (0, 0)][DBLP ] Conf ] Frank H. Hielscher , John C. Pagano Backdrive Stress-Testing of CMOS Gate Array Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Josef H. Hendriks Overdriving NMOS and CMOS VLSI Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Howard D. Helms Various Architectures of Systems for Measuring Early-Life Failure Rates of Semiconductor Components. [Citation Graph (0, 0)][DBLP ] Conf ] Jerry M. Soden , Charles F. Hawkins Electrical Characteristics and Testing Considerations for Gate Oxide Shorts in CMOS ICs. [Citation Graph (0, 0)][DBLP ] Conf ] Patrick P. Fasang , Michael A. Schuette , John Paul Shen , William A. Gwaltney Automated Design for Testability of Semicustom Integrated Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Robert J. Orsello Programmable Logic: Testability by Design. [Citation Graph (0, 0)][DBLP ] Conf ] Dong Sam Ha , Sudhakar M. Reddy On the Design of Testable Domino PLAs. [Citation Graph (0, 0)][DBLP ] Conf ] Hideo Fujiwara , Kewal K. Saluja , Kozo Kinoshita A Testable Design of Programmable Logic Arrays with Universal Control and Minimal Overhead. [Citation Graph (0, 0)][DBLP ] Conf ] James Jacob , Nripendra N. Biswas : A Testable PLA Design with Minimal Hardware and Test Set. [Citation Graph (0, 0)][DBLP ] Conf ] Albert Lam , Savio N. Chau , Huy Luong Design of a Class of Self-Exercising Combinational Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Martin I. Eiger , Michele J. Chabot Algorithms for High-Performance Fixture Wiring. [Citation Graph (0, 0)][DBLP ] Conf ] H. S. Lahman , C. L. Johnson A Computerized Solution to the Fixture-Wiring Problem. [Citation Graph (0, 0)][DBLP ] Conf ] Tim Moore , Stephen Garner Auto-Probing on the L200 Functional Tester. [Citation Graph (0, 0)][DBLP ] Conf ] James Congdon Driver/Sensor Design for High-Performance ATE. [Citation Graph (0, 0)][DBLP ] Conf ] T. Shiragasawa , M. Sugano , Yoshihisa Mano , M. Noyori An On-Lined Laser Probing System for Diagnosing Scaled VLSI. [Citation Graph (0, 0)][DBLP ] Conf ] Norio Kuji , Teruo Tamama Automated Fault Diagnostic EB Tester and Its Application to a 40K-Gate VLSI Circuit. [Citation Graph (0, 0)][DBLP ] Conf ] S. Daniel Lee , Lisa Deerr Li A Comprehensive Approach to Test Program Debugging for High Performance VLSI Test Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Brijendra Sharma , Colin McIntyre , Gerard Labonville , Jose Avila Integrated Test Program Development Package. [Citation Graph (0, 0)][DBLP ] Conf ] Arthur E. Downey Waveform: A Software Tool for Efficient Test Program Development. [Citation Graph (0, 0)][DBLP ] Conf ] Reed I. White TRS and DTS : IC Test Result Standards. [Citation Graph (0, 0)][DBLP ] Conf ] L. J. Falkenstrom , David C. Keezer , A. Patterson , Robert M. Rolfe , J. Wolcott Tester Independent Support Software System (TISSS). [Citation Graph (0, 0)][DBLP ] Conf ] David Giles , Kenneth R. Bowden , Mike Haney , Gregory A. Maston Maintaining Simulation Accuracy through Physical Device Models. [Citation Graph (0, 0)][DBLP ] Conf ] Jeremy Richman , Kenneth R. Bowden The Modern Fault Dictionary. [Citation Graph (0, 0)][DBLP ] Conf ] Ernst Ulrich Concurrent Simulation at the Switch, Gate, and Register Levels. [Citation Graph (0, 0)][DBLP ] Conf ] William A. Rogers , Jacob A. Abraham CHIEFS : A Concurrent, Hierarchical and Extensible Fault Simulator. [Citation Graph (0, 0)][DBLP ] Conf ] Masahiko Kawamura , Kanji Hirabayashi AFS : An Approximate Fault Simulator. [Citation Graph (0, 0)][DBLP ] Conf ] Zeev Barzilai , Vijay S. Iyengar , Barry K. Rosen , Gabriel M. Silberman Accurate Fault Modeling and Efficient Simulation of Differential CVS Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Yashwant K. Malaiya Faults in Microprogrammed and Hardwired Control. [Citation Graph (0, 0)][DBLP ] Conf ] Carl Staelin , Alexander Albicki Evaluation ot Monitor Complexity for Concurrently Testing Microprogrammed Control Units. [Citation Graph (0, 0)][DBLP ] Conf ] Raoul Velazco , Haissam Ziade , E. Kolokithas A Microprocessor Test Approach Allowing Fault Localization. [Citation Graph (0, 0)][DBLP ] Conf ] D. K. Verbeek , W. C. Bruce Testability Features of the MC68HC11. [Citation Graph (0, 0)][DBLP ] Conf ] Luis A. Basto , John R. Kuban Test Features ot the MC68881 Floating-Point Coprocessor. [Citation Graph (0, 0)][DBLP ] Conf ] Predrag G. Kovijanic , Ramesh G. Kulkarni Testability Analysis of Programmable Array Logic. [Citation Graph (0, 0)][DBLP ] Conf ] Balakrishnan Krishnamurthy , Richard Li-Cheng Sheng A New Approach to the Use of Testability Analysis in Test Generation. [Citation Graph (0, 0)][DBLP ] Conf ] John A. Waicukauski , Eric Lindbloom , Edward B. Eichelberger , Donato O. Forlenza , Tim McCarthy A Statistical Calculation of Fault Detection Probabilities By Fast Fault Simulation. [Citation Graph (0, 0)][DBLP ] Conf ] Franc Brglez A Fast Fault Grader: Analysis and Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Miron Abramovici Low-Cost Fault Simulation: Why, When and How. [Citation Graph (0, 0)][DBLP ] Conf ] Vishwani D. Agrawal STAFAN Takes a Middle Course. [Citation Graph (0, 0)][DBLP ] Conf ] Franc Brglez Fault Coverage Tools: Case Studies. [Citation Graph (0, 0)][DBLP ] Conf ] Prabhakar Goel , Chi-Lai Huang Statistical Fault Sampling and Full Fault Simulation. [Citation Graph (0, 0)][DBLP ] Conf ] Sharad C. Seth Predicting Fault Coverage from Probabilistic Testability. [Citation Graph (0, 0)][DBLP ] Conf ] D. Kazakos Statistical Failure Detection Methods for Linear Analog Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Gerard N. Stenbakken , T. Michael Souders : Modeling and Test Point Selection for Data Converter Testing. [Citation Graph (0, 0)][DBLP ] Conf ] Clyde Browning Testing A/D Converters on Microcomputers. [Citation Graph (0, 0)][DBLP ] Conf ] H. Kitayoshi , S. Sumida , K. Shirakawa , S. Takeshita DSP Synthesized Signal Source for Analog Testing Stimulus and New Test Method. [Citation Graph (0, 0)][DBLP ] Conf ] Brent Schusheim Employing Multiple Test Techniques for Complex Telecommunications Devices. [Citation Graph (0, 0)][DBLP ] Conf ] F. Matthiesen , Michael J. Ohletz Test of Digital Transversal Filters. [Citation Graph (0, 0)][DBLP ] Conf ] Patricia M. Ryan , A. Jesse Wilkinson Knowledge Acquisition for ATE Diagnosis. [Citation Graph (0, 0)][DBLP ] Conf ] Oliver Grillmeyer , A. Jesse Wilkinson The Design and Construction of a Rule Base and an Inference Engine for Test System Diagnosis. [Citation Graph (0, 0)][DBLP ] Conf ] Larry Apfelbaum An Expert System for In-Circuit Fault Diagnosis. [Citation Graph (0, 0)][DBLP ] Conf ] Stephen L. Lusky , T. Sridhar Detectable CMOS Faults in Switch-Level Simulation. [Citation Graph (0, 0)][DBLP ] Conf ] Kyushik Son Rule Based Testability Checker and Test Generator. [Citation Graph (0, 0)][DBLP ] Conf ] Frank F. Tsui The Cost and Speed Barriers in LSI/VLSI Testing : Can They Be Overcome By Testability Design ? [Citation Graph (0, 0)][DBLP ] Conf ] Ali Feizi , Damu Radhakrishnan Multiple Output Pass Networks: Design and Testing. [Citation Graph (0, 0)][DBLP ] Conf ] Bell Liu The Challenge of Configurable Logic Array Testing. [Citation Graph (0, 0)][DBLP ] Conf ] Tonysheng Lin , Stephen Y. H. Su VLSI Functional Test Pattern Generation: A Design and Implementation. [Citation Graph (0, 0)][DBLP ] Conf ] Uming Ko , Dinesh G. Patel , Francois J. Henley Contactless VLSI Laser Probing. [Citation Graph (0, 0)][DBLP ] Conf ] Robert W. Atherton , John L. Mudge Microprocessor Speed Optimization Using Pattern-Recognition Analysis of Parametric Test Data. [Citation Graph (0, 0)][DBLP ] Conf ] John D. Tobey Reducing Test Program Development Time for Memory Devices. [Citation Graph (0, 0)][DBLP ] Conf ] William P. Allaire Case Study: ATE Networking Using Peripheral Emulation. [Citation Graph (0, 0)][DBLP ] Conf ] Michael Dapron Linking Design Tools to In-Circuit Test Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Peter Hansen Converting Device Test Vectors to an In-Circuit Board Test Environment. [Citation Graph (0, 0)][DBLP ] Conf ] Steven R. Nelson Distributed Factory Data Management-Breaking the Network Bottleneck. [Citation Graph (0, 0)][DBLP ] Conf ] 