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Bernd Becker: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Tobias Schubert, Bernd Becker
    Parallel SAT Solving with Microcontrollers. [Citation Graph (0, 0)][DBLP]
    AACC, 2004, pp:59-67 [Conf]
  2. Tobias Schubert, Bernd Becker
    A Distributed SAT Solver for Microcontroller. [Citation Graph (0, 0)][DBLP]
    ARCS Workshops, 2004, pp:338-347 [Conf]
  3. Rolf Drechsler, Bernd Becker
    Learning heuristics by genetic algorithms. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1995, pp:- [Conf]
  4. Wolfgang Günther, Andreas Hett, Bernd Becker
    Application of linearly transformed BDDs in sequential verification. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:91-96 [Conf]
  5. Martin Keim, Nicole Drechsler, Bernd Becker
    Combining GAs and Symbolic Methods for High Quality Tests of Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1999, pp:315-318 [Conf]
  6. Christoph Scholl, Bernd Becker, Andreas Brogle
    The multiple variable order problem for binary decision diagrams: theory and practical application. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:85-90 [Conf]
  7. John P. Hayes, Ilia Polian, Bernd Becker
    Testing for Missing-Gate Faults in Reversible Circuits. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2004, pp:100-105 [Conf]
  8. Harry Hengster, Rolf Drechsler, Bernd Becker, Stefan Eckrich, Tonja Pfeiffer
    AND/EXOR based Synthesis of Testable KFDD-Circuits with Small Depth. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1996, pp:148-0 [Conf]
  9. Sandip Kundu, Piet Engelke, Ilia Polian, Bernd Becker
    On Detection of Resistive Bridging Defects by Low-Temperature and Low-Voltage Testing. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2005, pp:266-271 [Conf]
  10. Ilia Polian, Wolfgang Günther, Bernd Becker
    Efficient Pattern-Based Verification of Connections to IP Cores . [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2001, pp:443-448 [Conf]
  11. Ilia Polian, Thomas Fiehn, Bernd Becker, John P. Hayes
    A Family of Logical Fault Models for Reversible Circuits. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2005, pp:422-427 [Conf]
  12. Ilia Polian, Irith Pomeranz, Bernd Becker
    Exact Computation of Maximally Dominating Faults and Its Application to n-Detection Tests. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2002, pp:2-14 [Conf]
  13. Ralf Wimmer, Marc Herbstritt, Holger Hermanns, Kelley Strampp, Bernd Becker
    Sigref- A Symbolic Bisimulation Tool Box. [Citation Graph (0, 0)][DBLP]
    ATVA, 2006, pp:477-492 [Conf]
  14. Bernd Becker, Uwe Sparmann
    Regular Structures and Testing: RCC-Adders. [Citation Graph (0, 0)][DBLP]
    AWOC, 1988, pp:288-300 [Conf]
  15. Bernd Becker, Günter Hotz, Reiner Kolla, Paul Molitor, Hans-Georg Osthof
    Hierarchical Design Based on a Calculus of Nets. [Citation Graph (0, 0)][DBLP]
    DAC, 1987, pp:649-653 [Conf]
  16. Rolf Drechsler, Andisheh Sarabi, Michael Theobald, Bernd Becker, Marek A. Perkowski
    Efficient Representation and Manipulation of Switching Functions Based on Ordered Kronecker Functional Decision Diagrams. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:415-419 [Conf]
  17. Andreas Hett, Christoph Scholl, Bernd Becker
    Distance driven finite state machine traversal. [Citation Graph (0, 0)][DBLP]
    DAC, 2000, pp:39-42 [Conf]
  18. Rolf Krieger, Bernd Becker, Martin Keim
    Symbolic Fault Simulation for Sequential Circuits and the Multiple Observation Time Test Strategy. [Citation Graph (0, 0)][DBLP]
    DAC, 1995, pp:339-344 [Conf]
  19. Christoph Scholl, Bernd Becker
    Checking Equivalence for Partial Implementations. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:238-243 [Conf]
  20. Ilia Polian, Bernd Becker, Sudhakar M. Reddy
    Evolutionary Optimization of Markov Sources for Pseudo Random Scan BIST. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:11184-11185 [Conf]
  21. Ilia Polian, Alejandro Czutro, Bernd Becker
    Evolutionary Optimization in Code-Based Test Compression. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:1124-1129 [Conf]
  22. Christoph Scholl, Bernd Becker
    On the Generation of Multiplexer Circuits for Pass Transistor Logic. [Citation Graph (0, 0)][DBLP]
    DATE, 2000, pp:372-0 [Conf]
  23. Marc Herbstritt, Bernd Becker, Erika Ábrahám, Christian Herde
    On Variable Selection in SAT-LP-based Bounded Model Checking of Linear Hybrid Automata. [Citation Graph (0, 0)][DBLP]
    DDECS, 2007, pp:391-396 [Conf]
  24. Jochen Eisinger, Ilia Polian, Bernd Becker, Alexander Metzner, Stephan Thesing, Reinhard Wilhelm
    Automatic Identification of Timing Anomalies for Cycle-Accurate Worst-Case Execution Time Analysis. [Citation Graph (0, 0)][DBLP]
    DDECS, 2006, pp:15-20 [Conf]
  25. Ralf Wimmer, Marc Herbstritt, Bernd Becker
    Minimization of Large State Spaces using Symbolic Branching Bisimulation. [Citation Graph (0, 0)][DBLP]
    DDECS, 2006, pp:9-14 [Conf]
  26. Ilia Polian, Bernd Becker, Masato Nakasato, Satoshi Ohtake, Hideo Fujiwara
    Low-Cost Hardening of Image Processing Applications Against Soft Errors. [Citation Graph (0, 0)][DBLP]
    DFT, 2006, pp:274-279 [Conf]
  27. Bernd Becker, Thomas Eschbach, Rolf Drechsler, Wolfgang Günther
    Greedy_IIP: Partitioning Large Graphs by Greedy Iterative Improvement. [Citation Graph (0, 0)][DBLP]
    DSD, 2001, pp:54-61 [Conf]
  28. Nicole Drechsler, Rolf Drechsler, Bernd Becker
    Multi-objective Optimisation Based on Relation Favour. [Citation Graph (0, 0)][DBLP]
    EMO, 2001, pp:154-166 [Conf]
  29. Bernd Becker, Rolf Drechsler
    Testability of Circuits Derived from Functional Decision Diagrams. [Citation Graph (0, 0)][DBLP]
    EDAC-ETC-EUROASIC, 1994, pp:667- [Conf]
  30. Ralf Hahn, Rolf Krieger, Bernd Becker
    A Hierarchical Approach to Fault Collapsing. [Citation Graph (0, 0)][DBLP]
    EDAC-ETC-EUROASIC, 1994, pp:171-176 [Conf]
  31. Rolf Drechsler, Nicole Drechsler, Elke Mackensen, Tobias Schubert, Bernd Becker
    Design Reuse by Modularity: A Scalable Dynamical (Re)Configurable Multiprocessor System. [Citation Graph (0, 0)][DBLP]
    EUROMICRO, 2000, pp:1425-0 [Conf]
  32. Rolf Drechsler, Wolfgang Günther, Bernd Becker
    Testability of Circuits Derived from Lattice Diagrams. [Citation Graph (0, 0)][DBLP]
    EUROMICRO, 2000, pp:1188-1192 [Conf]
  33. Wolfgang Günther, Nicole Drechsler, Rolf Drechsler, Bernd Becker
    Verification of Designs Containing Black Boxes. [Citation Graph (0, 0)][DBLP]
    EUROMICRO, 2000, pp:1100-1105 [Conf]
  34. Bernd Becker, Hans-Ulrich Simon
    How Robust Is the n-Cube? (Extended Abstract) [Citation Graph (0, 0)][DBLP]
    FOCS, 1986, pp:283-291 [Conf]
  35. Harry Hengster, Bernd Becker
    Synthesis of Circuits Derived from Decision Diagrams - Combining Small Delay and Testability. [Citation Graph (0, 0)][DBLP]
    FTCS, 1999, pp:268-275 [Conf]
  36. Rolf Krieger, Bernd Becker, Can Ökmen
    OBDD-based Optimization of Input Probabilities for Weighted Random Pattern Generation. [Citation Graph (0, 0)][DBLP]
    FTCS, 1995, pp:120-129 [Conf]
  37. Rolf Krieger, Bernd Becker, R. Sinkovic
    A BDD - based Algorithm for Computation of Exact Fault Detection Probabilities. [Citation Graph (0, 0)][DBLP]
    FTCS, 1993, pp:186-195 [Conf]
  38. Nicole Drechsler, Rolf Drechsler, Bernd Becker
    Multi-objected Optimization in Evolutionary Algorithms Using Satisfiability Classes. [Citation Graph (0, 0)][DBLP]
    Fuzzy Days, 1999, pp:108-117 [Conf]
  39. Frank Schmiedle, Daniel Große, Rolf Drechsler, Bernd Becker
    Too Much Knowledge Hurts: Acceleration of Genetic Programs for Learning Heuristics. [Citation Graph (0, 0)][DBLP]
    Fuzzy Days, 2001, pp:479-491 [Conf]
  40. Thomas Eschbach, Wolfgang Günther, Rolf Drechsler, Bernd Becker
    Crossing Reduction by Windows Optimization. [Citation Graph (0, 0)][DBLP]
    Graph Drawing, 2002, pp:285-294 [Conf]
  41. Wolfgang Günther, Robby Schönfeld, Bernd Becker, Paul Molitor
    k-Layer Straightline Crossing Minimization by Speeding Up Sifting. [Citation Graph (0, 0)][DBLP]
    Graph Drawing, 2000, pp:253-258 [Conf]
  42. Tobias Schubert, Elke Mackensen, Nicole Drechsler, Rolf Drechsler, Bernd Becker
    Specialized Hardware for Implementation of Evolutionary Algorithms. [Citation Graph (0, 0)][DBLP]
    GECCO, 2000, pp:369- [Conf]
  43. Thomas Eschbach, Wolfgang Günther, Bernd Becker
    Orthogonal hypergraph routing for improved visibility. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2004, pp:385-388 [Conf]
  44. Ralf Wimmer, Marc Herbstritt, Bernd Becker
    Optimization techniques for BDD-based bisimulation computation. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:405-410 [Conf]
  45. Bernd Becker, Rolf Drechsler, Michael Theobald
    OKFDDs versus OBDDs and OFDDs. [Citation Graph (0, 0)][DBLP]
    ICALP, 1995, pp:475-486 [Conf]
  46. Christoph Scholl, Bernd Becker, Thomas M. Weis
    Word-level decision diagrams, WLCDs and division. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:672-677 [Conf]
  47. Christoph Scholl, Rolf Drechsler, Bernd Becker
    Functional simulation using binary decision diagrams. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1997, pp:8-12 [Conf]
  48. Bernd Becker, Rolf Drechsler
    OFDD Based Minimization of Fixed Polarity Reed-Muller Expressions Using Hybrid Genetic Algorithms. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:106-110 [Conf]
  49. Rolf Drechsler, Bernd Becker
    Dynamic minimization of OKFDDs. [Citation Graph (0, 0)][DBLP]
    ICCD, 1995, pp:602-0 [Conf]
  50. Per Lindgren, Rolf Drechsler, Bernd Becker
    Minimization of Ordered Pseudo Kronecker Decision Diagrams. [Citation Graph (0, 0)][DBLP]
    ICCD, 2000, pp:504-0 [Conf]
  51. Per Lindgren, Rolf Drechsler, Bernd Becker
    Synthesis of Pseudo Kronecker Lattice Diagrams. [Citation Graph (0, 0)][DBLP]
    ICCD, 1999, pp:307-310 [Conf]
  52. Christoph Scholl, Bernd Becker
    Checking Equivalence for Circuits Containing Incompletely Specified Boxes. [Citation Graph (0, 0)][DBLP]
    ICCD, 2002, pp:56-63 [Conf]
  53. Ilia Polian, Bernd Becker
    Stop & Go BIST. [Citation Graph (0, 0)][DBLP]
    IOLTW, 2002, pp:147-151 [Conf]
  54. Ilia Polian, Martin Keim, Nicolai Mallig, Bernd Becker
    Sequential n -Detection Criteria: Keep It Simple. [Citation Graph (0, 0)][DBLP]
    IOLTW, 2002, pp:189- [Conf]
  55. Thomas Eschbach, Rolf Dreschler, Bernd Becker
    Placement and routing optimization for circuits derived from BDDs. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2004, pp:229-232 [Conf]
  56. Christoph Scholl, Marc Herbstritt, Bernd Becker
    Exploiting don't cares to minimize *BMDs. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:191-194 [Conf]
  57. Rolf Drechsler, Marc Herbstritt, Bernd Becker
    Grouping heuristics for word-level decision diagrams. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 1999, pp:411-414 [Conf]
  58. Frank Schmiedle, Rolf Drechsler, Bernd Becker
    Exact channel routing using symbolic representation. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 1999, pp:394-397 [Conf]
  59. Bernd Becker, Rolf Drechsler
    Efficient Graph Based Representation of Multi-Valued Functions with an Application to Genetic Algorithms. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1994, pp:65-72 [Conf]
  60. Rolf Drechsler, Rolf Krieger, Bernd Becker
    Random Pattern Fault Simulation in Multi-Valued Circuits. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1995, pp:98-103 [Conf]
  61. Rolf Drechsler, Martin Keim, Bernd Becker
    Sympathy-MV: Fast Exact Minimization of Fixed Polarity Multi-Valued Linear Expressions. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1997, pp:66-0 [Conf]
  62. Rolf Drechsler, Martin Keim, Bernd Becker
    Fault Simulation in Sequential Multi-Valued Logic Networks. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1997, pp:145-0 [Conf]
  63. Martin Keim, Nicole Drechsler, Rolf Drechsler, Bernd Becker
    Test Generation for (Sequential) Multi-Valued Logic Networks based on Genetic Algorithm. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1998, pp:215-0 [Conf]
  64. Per Lindgren, Rolf Drechsler, Bernd Becker
    Look-up Table FPGA Synthesis from Minimized Multi-Valued Pseudo Kronecker Expressions. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1998, pp:95-0 [Conf]
  65. Ilia Polian, Piet Engelke, Bernd Becker
    Efficient Bridging Fault Simulation of Sequential Circuits Based on Multi-Valued Logics. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2002, pp:216-0 [Conf]
  66. Frank Schmiedle, Daniel Unruh, Bernd Becker
    Exact switchbox routing with search space reduction. [Citation Graph (0, 0)][DBLP]
    ISPD, 2000, pp:26-32 [Conf]
  67. Tobias Schubert, Bernd Becker
    Lemma Exchange in a Microcontroller Based Parallel SAT Solver. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2005, pp:142-147 [Conf]
  68. Piet Engelke, Ilia Polian, Michel Renovell, Bernd Becker
    Simulating Resistive Bridging and Stuck-At Faults. [Citation Graph (0, 0)][DBLP]
    ITC, 2003, pp:1051-1059 [Conf]
  69. Harry Hengster, Uwe Sparmann, Bernd Becker, Sudhakar M. Reddy
    Local Transformations and Robust Dependent Path Delay. [Citation Graph (0, 0)][DBLP]
    ITC, 1996, pp:347-356 [Conf]
  70. Rolf Krieger, Bernd Becker, Martin Keim
    A Hybrid Fault Simulator for Synchronous Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    ITC, 1994, pp:614-623 [Conf]
  71. Yuyi Tang, Hans-Joachim Wunderlich, Harald P. E. Vranken, Friedrich Hapke, Michael Wittke, Piet Engelke, Ilia Polian, Bernd Becker
    X-Masking During Logic BIST and Its Impact on Defect Coverage. [Citation Graph (0, 0)][DBLP]
    ITC, 2004, pp:442-451 [Conf]
  72. Bernd Becker, Rolf Drechsler, Ralph Werchner
    On the Relation Betwen BDDs and FDDs. [Citation Graph (0, 0)][DBLP]
    LATIN, 1995, pp:72-83 [Conf]
  73. Bernd Becker
    Efficient Testing of Optimal Time Adders (Extended Abstract). [Citation Graph (0, 0)][DBLP]
    MFCS, 1986, pp:218-229 [Conf]
  74. Bernd Becker, Joachim Hartmann
    Some Remarks on the Test Complexity of Iterative Logic Arrays. [Citation Graph (0, 0)][DBLP]
    MFCS, 1992, pp:142-152 [Conf]
  75. Marc Herbstritt, Bernd Becker
    On SAT-based Bounded Invariant Checking of Blackbox Designs. [Citation Graph (0, 0)][DBLP]
    MTV, 2005, pp:23-28 [Conf]
  76. Marc Herbstritt, Thomas Kmieciak, Bernd Becker
    On the Impact of Structural Circuit Partitioning on SAT-Based Combinational Circuit Verification. [Citation Graph (0, 0)][DBLP]
    MTV, 2004, pp:50-55 [Conf]
  77. Tobias Schubert, Bernd Becker
    PICHAFF2 - A Hierarchical Parallel SAT Solver. [Citation Graph (0, 0)][DBLP]
    MTV, 2004, pp:56-61 [Conf]
  78. Tobias Schubert, Matthew D. T. Lewis, Bernd Becker
    PaMira - A Parallel SAT Solver with Knowledge Sharing. [Citation Graph (0, 0)][DBLP]
    MTV, 2005, pp:29-36 [Conf]
  79. Marc Herbstritt, Bernd Becker, Christoph Scholl
    Advanced SAT-Techniques for Bounded Model Checking of Blackbox Designs. [Citation Graph (0, 0)][DBLP]
    MTV, 2006, pp:37-44 [Conf]
  80. Tobias Schubert, Bernd Becker
    Knowledge Sharing in a Microcontroller based Parallel SAT Solver. [Citation Graph (0, 0)][DBLP]
    PDPTA, 2005, pp:1049-1055 [Conf]
  81. Jochen Eisinger, Peter Winterer, Bernd Becker
    Securing Wireless Networks in a University Environment. [Citation Graph (0, 0)][DBLP]
    PerCom Workshops, 2005, pp:312-316 [Conf]
  82. Rolf Drechsler, Nicole Göckel, Bernd Becker
    Learning Heuristics for OBDD Minimization by Evolutionary Algorithms. [Citation Graph (0, 0)][DBLP]
    PPSN, 1996, pp:730-739 [Conf]
  83. Eckard Böde, Marc Herbstritt, Holger Hermanns, Sven Johr, Thomas Peikenkamp, Reza Pulungan, Ralf Wimmer, Bernd Becker
    Compositional Performability Evaluation for STATEMATE. [Citation Graph (0, 0)][DBLP]
    QEST, 2006, pp:167-178 [Conf]
  84. Marc Herbstritt, Bernd Becker
    Conflict-Based Selection of Branching Rules. [Citation Graph (0, 0)][DBLP]
    SAT, 2003, pp:441-451 [Conf]
  85. Matthew D. T. Lewis, Tobias Schubert, Bernd Becker
    Early Conflict Detection Based BCP for SAT Solving. [Citation Graph (0, 0)][DBLP]
    SAT, 2004, pp:- [Conf]
  86. Matthew D. T. Lewis, Tobias Schubert, Bernd Becker
    Speedup Techniques Utilized in Modern SAT Solvers. [Citation Graph (0, 0)][DBLP]
    SAT, 2005, pp:437-443 [Conf]
  87. Bernd Becker, Joachim Hartmann
    Optimal-Time Multipliers and C-Testability. [Citation Graph (0, 0)][DBLP]
    SPAA, 1990, pp:146-154 [Conf]
  88. Bernd Becker
    Synthesis for Testability: Binary Decision Diagrams. [Citation Graph (0, 0)][DBLP]
    STACS, 1992, pp:501-512 [Conf]
  89. Bernd Becker, Reiner Kolla
    On the Construction of Optimal Time Adders (Extended Abstract). [Citation Graph (0, 0)][DBLP]
    STACS, 1988, pp:18-28 [Conf]
  90. Bernd Becker, Hans-Georg Osthof
    Layouts with Wires of Balanced Length. [Citation Graph (0, 0)][DBLP]
    STACS, 1985, pp:21-31 [Conf]
  91. Rolf Drechsler, Bernd Becker, Stefan Ruppertz
    Manipulation Algorithms for K*BMDs. [Citation Graph (0, 0)][DBLP]
    TACAS, 1997, pp:4-18 [Conf]
  92. Bernd Becker
    On the crossing-free, rectangular embedding of weighted graphs in the plane. [Citation Graph (0, 0)][DBLP]
    Theoretical Computer Science, 1983, pp:61-72 [Conf]
  93. Thomas Eschbach, Wolfgang Günther, Bernd Becker
    Cross Reduction for Orthogonal Circuit Visualization. [Citation Graph (0, 0)][DBLP]
    VLSI, 2003, pp:107-113 [Conf]
  94. Ilia Polian, Bernd Becker
    Reducing ATE Cost in System-on-Chip Test. [Citation Graph (0, 0)][DBLP]
    VLSI-SOC, 2003, pp:337-342 [Conf]
  95. Bernd Becker, Rolf Drechsler
    Decision Diagrams in Synthesis - Algorithms, Applications and Extensions. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:46-50 [Conf]
  96. Bernd Becker, Rolf Drechsler, Sudhakar M. Reddy
    (Quasi-) Linear Path Delay Fault Tests for Adders. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:101-105 [Conf]
  97. Bernd Becker, Rolf Krieger
    FAST-SC: Fast Fault Simulation in Synchronous Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1993, pp:128-131 [Conf]
  98. Thomas Eschbach, Wolfgang Günther, Bernd Becker
    Orthogonal Circuit Visualization Improved by Merging the Placement and Routing Phases. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2005, pp:433-438 [Conf]
  99. Harry Hengster, Rolf Drechsler, Bernd Becker
    Testability Properties of Local Circuit Transformations with Respect to the Robust Path-Delay-Fault Model. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1994, pp:123-126 [Conf]
  100. Erika Ábrahám, Bernd Becker, Felix Klaedtke, Martin Steffen
    Optimizing Bounded Model Checking for Linear Hybrid Systems. [Citation Graph (0, 0)][DBLP]
    VMCAI, 2005, pp:396-412 [Conf]
  101. Piet Engelke, Ilia Polian, Michel Renovell, Bharath Seshadri, Bernd Becker
    The Pros and Cons of Very-Low-Voltage Testing: An Analysis based on Resistive Bridging Faults. [Citation Graph (0, 0)][DBLP]
    VTS, 2004, pp:171-178 [Conf]
  102. Harry Hengster, Rolf Drechsler, Bernd Becker
    On the application of local circuit transformations with special emphasis on path delay fault testability. [Citation Graph (0, 0)][DBLP]
    VTS, 1995, pp:387-392 [Conf]
  103. Martin Keim, Bernd Becker, Birgitta Stenner
    On the (non-)resetability of synchronous sequential circuits. [Citation Graph (0, 0)][DBLP]
    VTS, 1996, pp:240-245 [Conf]
  104. Martin Keim, Michael Martin, Bernd Becker, Rolf Drechsler, Paul Molitor
    Polynomial Formal Verification of Multipliers. [Citation Graph (0, 0)][DBLP]
    VTS, 1997, pp:150-157 [Conf]
  105. Can Ökmen, Martin Keim, Rolf Krieger, Bernd Becker
    On Optimizing BIST-Architecture by Using OBDD-based Approaches and Genetic Algorithms. [Citation Graph (0, 0)][DBLP]
    VTS, 1997, pp:426-433 [Conf]
  106. Ilia Polian, Bernd Becker
    Multiple Scan Chain Design for Two-Pattern Testing. [Citation Graph (0, 0)][DBLP]
    VTS, 2001, pp:88-93 [Conf]
  107. Ilia Polian, Sandip Kundu, Jean Marc Galliere, Piet Engelke, Michel Renovell, Bernd Becker
    Resistive Bridge Fault Model Evolution from Conventional to Ultra Deep Submicron Technologies. [Citation Graph (0, 0)][DBLP]
    VTS, 2005, pp:343-348 [Conf]
  108. John P. Hayes, Ilia Polian, Bernd Becker
    An Analysis Framework for Transient-Error Tolerance. [Citation Graph (0, 0)][DBLP]
    VTS, 2007, pp:249-255 [Conf]
  109. Bernd Becker, Markus Behle, Friedrich Eisenbrand, Ralf Wimmer
    BDDs in a Branch and Cut Framework. [Citation Graph (0, 0)][DBLP]
    WEA, 2005, pp:452-463 [Conf]
  110. Bernd Becker
    An Easily Testable Optimal-Time VLSI-Multiplier. [Citation Graph (0, 0)][DBLP]
    Acta Inf., 1987, v:24, n:4, pp:363-380 [Journal]
  111. Rolf Drechsler, Bernd Becker, Stefan Ruppertz
    The K*BMD: A Verification Data Structure. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1997, v:14, n:2, pp:51-59 [Journal]
  112. Bernd Becker, Joachim Hartmann
    Optimal-Time Multipliers and C-Testability. [Citation Graph (0, 0)][DBLP]
    Elektronische Informationsverarbeitung und Kybernetik, 1990, v:26, n:10, pp:547-561 [Journal]
  113. Erika Ábrahám, Marc Herbstritt, Bernd Becker, Martin Steffen
    Bounded Model Checking with Parametric Data Structures. [Citation Graph (0, 0)][DBLP]
    Electr. Notes Theor. Comput. Sci., 2007, v:174, n:3, pp:3-16 [Journal]
  114. Bernd Becker, Rolf Drechsler, Michael Theobald
    On the Expressive Power of OKFDDs. [Citation Graph (0, 0)][DBLP]
    Formal Methods in System Design, 1997, v:11, n:1, pp:5-21 [Journal]
  115. Martin Keim, Rolf Drechsler, Bernd Becker, Michael Martin, Paul Molitor
    Polynomial Formal Verification of Multipliers. [Citation Graph (0, 0)][DBLP]
    Formal Methods in System Design, 2003, v:22, n:1, pp:39-58 [Journal]
  116. Christoph Scholl, Bernd Becker, Thomas M. Weis
    On WLCDs and the Complexity of Word-Level Decision Diagrams-A Lower Bound for Division. [Citation Graph (0, 0)][DBLP]
    Formal Methods in System Design, 2002, v:20, n:3, pp:311-326 [Journal]
  117. Bernd Becker, Uwe Sparmann
    A uniform test approach for RCC-adders. [Citation Graph (0, 0)][DBLP]
    Fundam. Inform., 1991, v:14, n:2, pp:185-219 [Journal]
  118. Bernd Becker, Rolf Drechsler, Ralph Werchner
    On the Relation between BDDs and FDDs. [Citation Graph (0, 0)][DBLP]
    Inf. Comput., 1995, v:123, n:2, pp:185-197 [Journal]
  119. Bernd Becker, Hans-Georg Osthof
    Layouts with Wires of Balanced Length [Citation Graph (0, 0)][DBLP]
    Inf. Comput., 1987, v:73, n:1, pp:45-59 [Journal]
  120. Bernd Becker, Hans-Ulrich Simon
    How Robust Is The n-Cube? [Citation Graph (0, 0)][DBLP]
    Inf. Comput., 1988, v:77, n:2, pp:162-178 [Journal]
  121. Günter Hotz, Bernd Becker, Reiner Kolla, Paul Molitor
    Ein logisch-topologischer Kalkül zur Konstruktion integrierter Schaltkreise, Teil I. [Citation Graph (0, 0)][DBLP]
    Inform., Forsch. Entwickl., 1986, v:1, n:1, pp:38-47 [Journal]
  122. Günter Hotz, Bernd Becker, Reiner Kolla, Paul Molitor
    Ein logisch-topologischer Kalkül zur Konstruktion integrierter Schaltkreise, Teil II. [Citation Graph (0, 0)][DBLP]
    Inform., Forsch. Entwickl., 1986, v:1, n:2, pp:72-82 [Journal]
  123. Bernd Becker
    Testing with decision diagrams. [Citation Graph (0, 0)][DBLP]
    Integration, 1998, v:26, n:1-2, pp:5-20 [Journal]
  124. Rolf Drechsler, Bernd Becker, Nicole Drechsler
    OKFDD minimization by genetic algorithms with application to circuit design. [Citation Graph (0, 0)][DBLP]
    Integration, 2000, v:28, n:2, pp:121-139 [Journal]
  125. Ilia Polian, Wolfgang Günther, Bernd Becker
    Pattern-based verification of connections to intellectual property cores. [Citation Graph (0, 0)][DBLP]
    Integration, 2003, v:35, n:1, pp:25-44 [Journal]
  126. Bernd Becker, Günter Hotz
    On the Optimal Layout of Planar Graphs with Fixed Boundary. [Citation Graph (0, 0)][DBLP]
    SIAM J. Comput., 1987, v:16, n:5, pp:946-972 [Journal]
  127. Bernd Becker
    Efficient Testing of Optimal Time Adders. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1988, v:37, n:9, pp:1113-1121 [Journal]
  128. Rolf Drechsler, Bernd Becker, Andrea Jahnke
    On Variable Ordering and Decomposition Type Choice in OKFDDs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1998, v:47, n:12, pp:1398-1403 [Journal]
  129. Rolf Drechsler, Michael Theobald, Bernd Becker
    Fast OFFD-Based Minimization of Fixed Polarity Reed-Muller Expressions. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1996, v:45, n:11, pp:1294-1299 [Journal]
  130. Frank Schmiedle, Rolf Drechsler, Bernd Becker
    Exact Routing with Search Space Reduction. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2003, v:52, n:6, pp:815-825 [Journal]
  131. Bernd Becker, Rolf Drechsler, Paul Molitor
    On the generation of area-time optimal testable adders. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:9, pp:1049-1066 [Journal]
  132. Rolf Drechsler, Bernd Becker
    Sympathy: fast exact minimization of fixed polarity Reed-Muller expressions for symmetric functions. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:1, pp:1-5 [Journal]
  133. Rolf Drechsler, Bernd Becker
    Ordered Kronecker functional decision diagrams-a data structure for representation and manipulation of Boolean functions. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:10, pp:965-973 [Journal]
  134. Piet Engelke, Ilia Polian, Michel Renovell, Bernd Becker
    Simulating Resistive-Bridging and Stuck-At Faults. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:10, pp:2181-2192 [Journal]
  135. Bernd Becker, Uwe Sparmann
    Computations over Finite Monoids and their Test Complexity. [Citation Graph (0, 0)][DBLP]
    Theor. Comput. Sci., 1991, v:84, n:2, pp:225-250 [Journal]
  136. Yuyi Tang, Hans-Joachim Wunderlich, Piet Engelke, Ilia Polian, Bernd Becker, Jürgen Schlöffel, Friedrich Hapke, Michael Wittke
    X-masking during logic BIST and its impact on defect coverage. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:2, pp:193-202 [Journal]
  137. Bernd Becker, Christian Dax, Jochen Eisinger, Felix Klaedtke
    LIRA: Handling Constraints of Linear Arithmetics over the Integers and the Reals. [Citation Graph (0, 0)][DBLP]
    CAV, 2007, pp:307-310 [Conf]
  138. Marc Herbstritt, Bernd Becker
    On Combining 01X-Logic and QBF. [Citation Graph (0, 0)][DBLP]
    EUROCAST, 2007, pp:531-538 [Conf]
  139. Ilia Polian, Damian Nowroth, Bernd Becker
    Identification of Critical Errors in Imaging Applications. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2007, pp:201-202 [Conf]
  140. Erika Ábrahám, Tobias Schubert, Bernd Becker, Martin Fränzle, Christian Herde
    Parallel SAT Solving in Bounded Model Checking. [Citation Graph (0, 0)][DBLP]
    FMICS/PDMC, 2006, pp:301-315 [Conf]
  141. Ilia Polian, Alejandro Czutro, Bernd Becker
    Evolutionary Optimization in Code-Based Test Compression [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]
  142. Bernd Becker, Ilia Polian, Sybille Hellebrand, Bernd Straube, Hans-Joachim Wunderlich
    DFG-Projekt RealTest - Test und Zuverlässigkeit nanoelektronischer Systeme (DFG-Project - Test and Reliability of Nano-Electronic Systems). [Citation Graph (0, 0)][DBLP]
    it - Information Technology, 2006, v:48, n:5, pp:304-0 [Journal]
  143. Bernd Becker, Andreas Podelski, Werner Damm, Martin Fränzle, Ernst-Rüdiger Olderog, Reinhard Wilhelm
    SFB/TR 14 AVACS - Automatic Verification and Analysis of Complex Systems (Der Sonderforschungsbereich/Transregio 14 AVACS - Automatische Verifikation und Analyse komplexer Systeme). [Citation Graph (0, 0)][DBLP]
    it - Information Technology, 2007, v:49, n:2, pp:118-0 [Journal]
  144. Ilia Polian, Piet Engelke, Michel Renovell, Bernd Becker
    Modeling Feedback Bridging Faults with Non-Zero Resistance. [Citation Graph (0, 0)][DBLP]
    J. Electronic Testing, 2005, v:21, n:1, pp:57-69 [Journal]
  145. Piet Engelke, Ilia Polian, Michel Renovell, Bernd Becker
    Automatic Test Pattern Generation for Resistive Bridging Faults. [Citation Graph (0, 0)][DBLP]
    J. Electronic Testing, 2006, v:22, n:1, pp:61-69 [Journal]

  146. Multithreaded SAT Solving. [Citation Graph (, )][DBLP]


  147. Dynamic Compaction in SAT-Based ATPG. [Citation Graph (, )][DBLP]


  148. Resistive Bridging Fault Simulation of Industrial Circuits. [Citation Graph (, )][DBLP]


  149. Fast and efficient construction of BDDs by reordering based synthesis. [Citation Graph (, )][DBLP]


  150. Testability of 2-level AND/EXOR circuits. [Citation Graph (, )][DBLP]


  151. Diagnosis of Realistic Defects Based on the X-Fault Model. [Citation Graph (, )][DBLP]


  152. Probabilistic Model Checking and Reliability of Results. [Citation Graph (, )][DBLP]


  153. On Reducing Circuit Malfunctions Caused by Soft Errors. [Citation Graph (, )][DBLP]


  154. A study of cognitive resilience in a JPEG compressor. [Citation Graph (, )][DBLP]


  155. Fast OFDD based minimization of fixed polarity Reed-Muller expressions. [Citation Graph (, )][DBLP]


  156. A graphical system for hierarchical specifications and checkups of VLSI circuits. [Citation Graph (, )][DBLP]


  157. Reducing temperature variability by routing heat pipes. [Citation Graph (, )][DBLP]


  158. Computation of minimal counterexamples by using black box techniques and symbolic methods. [Citation Graph (, )][DBLP]


  159. Power Droop Testing. [Citation Graph (, )][DBLP]


  160. Propositional approximations for bounded model checking of partial circuit designs. [Citation Graph (, )][DBLP]


  161. ATPG-based grading of strong fault-secureness. [Citation Graph (, )][DBLP]


  162. Scalable Calculation of Logical Masking Effects for Selective Hardening Against Soft Errors. [Citation Graph (, )][DBLP]


  163. Correctness Issues of Symbolic Bisimulation Computation for Markov Chains. [Citation Graph (, )][DBLP]


  164. Application of Lifting in Partial Design Analysis. [Citation Graph (, )][DBLP]


  165. Picoso - A Parallel Interval Constraint Solver. [Citation Graph (, )][DBLP]


  166. PaQuBE: Distributed QBF Solving with Advanced Knowledge Sharing. [Citation Graph (, )][DBLP]


  167. Encoding Techniques, Craig Interpolants and Bounded Model Checking for Incomplete Designs. [Citation Graph (, )][DBLP]


  168. Dependability Engineering of Silent Self-stabilizing Systems. [Citation Graph (, )][DBLP]


  169. TIGUAN: Thread-Parallel Integrated Test Pattern Generator Utilizing Satisfiability ANalysis. [Citation Graph (, )][DBLP]


  170. Counterexample Generation for Discrete-Time Markov Chains Using Bounded Model Checking. [Citation Graph (, )][DBLP]


  171. Automatic Test Pattern Generation for Interconnect Open Defects. [Citation Graph (, )][DBLP]


  172. A Definition and Classification of Timing Anomalies. [Citation Graph (, )][DBLP]


  173. Electromechanical Reliability Testing of Three-Axial Silicon Force Sensors [Citation Graph (, )][DBLP]


  174. Power Droop Testing. [Citation Graph (, )][DBLP]


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