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Vamsi Boppana: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Indradeep Ghosh, Krishna Sekar, Vamsi Boppana
    Design for Verification at the Register Transfer Level. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2002, pp:420-425 [Conf]
  2. Biplab K. Sikdar, Debesh K. Das, Vamsi Boppana, Cliff Yang, Sobhan Mukherjee, Parimal Pal Chaudhuri
    Cellular automata as a built in self test structure. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:319-324 [Conf]
  3. Vamsi Boppana, Sreeranga P. Rajan, Koichiro Takayama, Masahiro Fujita
    Model Checking Based on Sequential ATPG. [Citation Graph (0, 0)][DBLP]
    CAV, 1999, pp:418-430 [Conf]
  4. Vamsi Boppana, Rajarshi Mukherjee, Jawahar Jain, Masahiro Fujita, Pradeep Bollineni
    Multiple Error Diagnosis Based on Xlists. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:660-665 [Conf]
  5. Hiroaki Yoshida, Kaushik De, Vamsi Boppana
    Accurate pre-layout estimation of standard cell characteristics. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:208-211 [Conf]
  6. Vamsi Boppana, Prashant Saxena, Prithviraj Banerjee, W. Kent Fuchs, C. L. Liu
    A Parallel Algorithm for the Technology Mapping of LUT-Based FPGAs. [Citation Graph (0, 0)][DBLP]
    Euro-Par, Vol. I, 1996, pp:828-831 [Conf]
  7. Vamsi Boppana, Ismed Hartanto, W. Kent Fuchs
    Fault Diagnosis Using State Information. [Citation Graph (0, 0)][DBLP]
    FTCS, 1996, pp:96-103 [Conf]
  8. Vamsi Boppana, W. Kent Fuchs
    Fault dictionary compaction by output sequence removal. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1994, pp:576-579 [Conf]
  9. Vamsi Boppana, W. Kent Fuchs
    Integrated fault diagnosis targeting reduced simulation. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1996, pp:681-684 [Conf]
  10. Vamsi Boppana, W. Kent Fuchs
    Dynamic fault collapsing and diagnostic test pattern generation for sequential circuits. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:147-154 [Conf]
  11. Ismed Hartanto, Vamsi Boppana, W. Kent Fuchs
    Identification of unsettable flip-flops for partial scan and faster ATPG. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1996, pp:63-66 [Conf]
  12. Srivaths Ravi, Niraj K. Jha, Indradeep Ghosh, Vamsi Boppana
    A Technique for Identifying RTL and Gate-Level Correspondences. [Citation Graph (0, 0)][DBLP]
    ICCD, 2000, pp:591-0 [Conf]
  13. Vamsi Boppana, W. Kent Fuchs
    Partial Scan Design Based on State Transition Modeling. [Citation Graph (0, 0)][DBLP]
    ITC, 1996, pp:538-547 [Conf]
  14. Vamsi Boppana, Masahiro Fujita
    Modeling the unknown! Towards model-independent fault and error diagnosis. [Citation Graph (0, 0)][DBLP]
    ITC, 1998, pp:1094-0 [Conf]
  15. Ismed Hartanto, Vamsi Boppana, W. Kent Fuchs
    Diagnostic Fault Equivalence Identification Using Redundancy Information and Structural Analysis. [Citation Graph (0, 0)][DBLP]
    ITC, 1996, pp:294-302 [Conf]
  16. Vamsi Boppana, Indradeep Ghosh, Rajarshi Mukherjee, Jawahar Jain, Masahiro Fujita
    Hierarchical Error Diagnosis Targeting RTL Circuits. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2000, pp:436-441 [Conf]
  17. Vamsi Boppana, Ismed Hartanto, W. Kent Fuchs
    Characterization and Implicit Identification of Sequential Indistinguishability. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:376-380 [Conf]
  18. Indradeep Ghosh, Krishna Sekar, Vamsi Boppana
    Design for Verification at the Register Transfer Level. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:420-425 [Conf]
  19. S. Nandi, Vamsi Boppana, Parimal Pal Chaudhuri
    A CAD Tool for Design of On-Chip Store & Generate Scheme. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1994, pp:169-174 [Conf]
  20. S. Nandi, Vamsi Boppana, Supratik Chakraborty, Parimal Pal Chaudhuri, Samir Roy
    Delay Fault Test Generation with Cellular Automata. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1993, pp:281-286 [Conf]
  21. Biplab K. Sikdar, Kolin Paul, Gosta Pada Biswas, Parimal Pal Chaudhuri, Vamsi Boppana, Cliff Yang, Sobhan Mukherjee
    Theory and Application of GF(2p) Cellular Automata as On-chip Test Pattern Generator. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2000, pp:556-561 [Conf]
  22. Vamsi Boppana, Ismed Hartanto, W. Kent Fuchs
    Full fault dictionary storage based on labeled tree encoding. [Citation Graph (0, 0)][DBLP]
    VTS, 1996, pp:174-179 [Conf]
  23. Enamul Amyeen, W. Kent Fuchs, Irith Pomeranz, Vamsi Boppana
    Fault Equivalence Identification Using Redundancy Information and Static and Dynamic Extraction. [Citation Graph (0, 0)][DBLP]
    VTS, 2001, pp:124-130 [Conf]
  24. Enamul Amyeen, W. Kent Fuchs, Irith Pomeranz, Vamsi Boppana
    Implication and Evaluation Techniques for Proving Fault Equivalence. [Citation Graph (0, 0)][DBLP]
    VTS, 1999, pp:201-213 [Conf]
  25. Ismed Hartanto, Vamsi Boppana, Janak H. Patel, W. Kent Fuchs
    Diagnostic Test Pattern Generation for Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    VTS, 1997, pp:196-202 [Conf]
  26. Ankur Jain, Vamsi Boppana, Rajarshi Mukherjee, Jawahar Jain, Masahiro Fujita, Michael S. Hsiao
    Testing, Verification, and Diagnosis in the Presence of Unknowns. [Citation Graph (0, 0)][DBLP]
    VTS, 2000, pp:263-270 [Conf]
  27. Ankur Jain, Michael S. Hsiao, Vamsi Boppana, Masahiro Fujita
    On the Evaluation of Arbitrary Defect Coverage of Test Sets. [Citation Graph (0, 0)][DBLP]
    VTS, 1999, pp:426-432 [Conf]
  28. Rob Roy, Debashis Bhattacharya, Vamsi Boppana
    Transistor-Level Optimization of Digital Designs with Flex Cells. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 2005, v:38, n:2, pp:53-61 [Journal]
  29. Enamul Amyeen, W. Kent Fuchs, Irith Pomeranz, Vamsi Boppana
    Fault equivalence identification in combinational circuits using implication and evaluation techniques. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:7, pp:922-936 [Journal]
  30. Srivaths Ravi, Indradeep Ghosh, Vamsi Boppana, Niraj K. Jha
    Fault-diagnosis-based technique for establishing RTL and gate-levelcorrespondences. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:12, pp:1414-1425 [Journal]

  31. Low power chips: a fabless asic perspective. [Citation Graph (, )][DBLP]


  32. Implementing the Best Processor Cores. [Citation Graph (, )][DBLP]


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