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Peter A. Beerel :
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Peter A. Beerel , Aiguo Xie Performance Analysis of Asynchronous Circuits Using Markov Chains. [Citation Graph (0, 0)][DBLP ] Concurrency and Hardware Design, 2002, pp:313-344 [Conf ] Sunan Tugsinavisut , Roger Su , Peter A. Beerel High-level Synthesis for Highly Concurrent Hardware Systems. [Citation Graph (0, 0)][DBLP ] ACSD, 2006, pp:79-90 [Conf ] Peter A. Beerel , Ken S. Stevens , Hoshik Kim Relative Timing Based Verification of Timed Circuits and Systems. [Citation Graph (0, 0)][DBLP ] ASYNC, 2002, pp:115-0 [Conf ] Wei-Chun Chou , Peter A. Beerel , Ran Ginosar , Rakefet Kol , Chris J. Myers , Shai Rotem , Ken S. Stevens , Kenneth Y. Yun Average-Case Optimized Technology Mapping of One-Hot Domino CircuitsAverage-Case Optimized Transistor-Level Technology Mapping of Extended Burst-Mode Circuits. [Citation Graph (0, 0)][DBLP ] ASYNC, 1998, pp:80-0 [Conf ] Marcos Ferretti , Recep O. Ozdag , Peter A. Beerel High Performance Asynchronous ASIC Back-End Design Flow Using Single-Track Full-Buffer Standard Cells. [Citation Graph (0, 0)][DBLP ] ASYNC, 2004, pp:95-105 [Conf ] Pankaj Golani , Georgios D. Dimou , Mallika Prakash , Peter A. Beerel Design of a High-Speed Asynchronous Turbo Decoder. [Citation Graph (0, 0)][DBLP ] ASYNC, 2007, pp:49-59 [Conf ] Aiguo Xie , Peter A. Beerel Symbolic Techniques for Performance Analysis of Timed Systems Based on Average Time Separation of Events. [Citation Graph (0, 0)][DBLP ] ASYNC, 1997, pp:64-75 [Conf ] Aiguo Xie , Peter A. Beerel Accelerating Markovian Analysis of Asynchronous Systems using String- based State Compression. [Citation Graph (0, 0)][DBLP ] ASYNC, 1998, pp:247-0 [Conf ] Aiguo Xie , Sangyun Kim , Peter A. Beerel Bounding Average Time Separations of Events in Stochastic Timed Petri Nets with Choice. [Citation Graph (0, 0)][DBLP ] ASYNC, 1999, pp:94-107 [Conf ] Chris J. Myers , Peter A. Beerel , Teresa H. Y. Meng Technology mapping of timed circuits. [Citation Graph (0, 0)][DBLP ] ASYNC, 1995, pp:138-0 [Conf ] Steven M. Nowick , Kenneth Y. Yun , Ayoob E. Dooply , Peter A. Beerel Speculative Completion for the Design of High-Performance Asynchronous Dynamic Adders. [Citation Graph (0, 0)][DBLP ] ASYNC, 1997, pp:210-0 [Conf ] Kenneth Y. Yun , Ayoob E. Dooply , Julio Arceo , Peter A. Beerel , Vida Vakilotojar The Design and Verification of A High-Performance Low-Control-Overhead Asynchronous Differential Equation Solver. [Citation Graph (0, 0)][DBLP ] ASYNC, 1997, pp:140-0 [Conf ] Recep O. Ozdag , Peter A. Beerel High-Speed QDI Asynchronous Pipelines. [Citation Graph (0, 0)][DBLP ] ASYNC, 2002, pp:13-22 [Conf ] Recep O. Ozdag , Peter A. Beerel A Channel Based Asynchronous Low Power High Performance Standard-Cell Based Sequential Decoder Implemented with QDI Templates. [Citation Graph (0, 0)][DBLP ] ASYNC, 2004, pp:187-197 [Conf ] Shai Rotem , Ken S. Stevens , Charles Dike , Marly Roncken , Boris Agapiev , Ran Ginosar , Rakefet Kol , Peter A. Beerel , Chris J. Myers , Kenneth Y. Yun RAPPID: An Asynchronous Instruction Length Decoder. [Citation Graph (0, 0)][DBLP ] ASYNC, 1999, pp:60-70 [Conf ] Peter A. Beerel , Nam-Hoon Kim , Andrew Lines , Mike Davies Slack Matching Asynchronous Designs. [Citation Graph (0, 0)][DBLP ] ASYNC, 2006, pp:184-194 [Conf ] Hüsnü Yenigün , Vladimir Levin , Doron Peled , Peter A. Beerel Hazard-Freedom Checking in Speed-Independent Systems. [Citation Graph (0, 0)][DBLP ] CHARME, 1999, pp:317-320 [Conf ] Peter A. Beerel , Teresa H. Y. Meng Testability of Asynchronous Timed Control Circuits with Delay Assumptions. [Citation Graph (0, 0)][DBLP ] DAC, 1991, pp:446-451 [Conf ] Youpyo Hong , Peter A. Beerel , Jerry R. Burch , Kenneth L. McMillan Safe BDD Minimization Using Don't Cares. [Citation Graph (0, 0)][DBLP ] DAC, 1997, pp:208-213 [Conf ] Youpyo Hong , Peter A. Beerel , Luciano Lavagno , Ellen Sentovich Don't Care-Based BDD Minimization for Embedded Software. [Citation Graph (0, 0)][DBLP ] DAC, 1998, pp:506-509 [Conf ] Aiguo Xie , Peter A. Beerel Efficient State Classification of Finite State Markov Chains. [Citation Graph (0, 0)][DBLP ] DAC, 1998, pp:605-610 [Conf ] Marcos Ferretti , Peter A. Beerel Single-Track Asynchronous Pipeline Templates Using 1-of-N Encoding. [Citation Graph (0, 0)][DBLP ] DATE, 2002, pp:1008-1015 [Conf ] Youpyo Hong , Peter A. Beerel Symbolic Reachability Analysis of Large Finite State Machines Using Don't Cares. [Citation Graph (0, 0)][DBLP ] DATE, 1999, pp:13-0 [Conf ] Recep O. Ozdag , Peter A. Beerel , Montek Singh , Steven M. Nowick High-Speed Non-Linear Asynchronous Pipelines. [Citation Graph (0, 0)][DBLP ] DATE, 2002, pp:1000-1007 [Conf ] Sunan Tugsinavisut , Peter A. Beerel Control Circuit Templates for Asynchronous Bundled-Data Pipelines. [Citation Graph (0, 0)][DBLP ] DATE, 2002, pp:1098- [Conf ] Peter A. Beerel , Jerry R. Burch , Teresa H. Y. Meng Efficient verification of determinate speed-independent circuits. [Citation Graph (0, 0)][DBLP ] ICCAD, 1993, pp:261-267 [Conf ] Peter A. Beerel , Teresa H. Y. Meng Automatic gate-level synthesis of speed-independent circuits. [Citation Graph (0, 0)][DBLP ] ICCAD, 1992, pp:581-586 [Conf ] Peter A. Beerel , Kenneth Y. Yun , Steven M. Nowick , Pei-Chuan Yeh Estimation and bounding of energy consumption in burst-mode control circuits. [Citation Graph (0, 0)][DBLP ] ICCAD, 1995, pp:26-33 [Conf ] Sangyun Kim , Peter A. Beerel Pipeline Optimization for Asynchronous Circuits: Complexity Analysis and an Efficient Optimal Algorithm. [Citation Graph (0, 0)][DBLP ] ICCAD, 2000, pp:296-302 [Conf ] Aiguo Xie , Peter A. Beerel Implicit enumeration of strongly connected components. [Citation Graph (0, 0)][DBLP ] ICCAD, 1999, pp:37-40 [Conf ] Sunan Tugsinavisut , Suwicha Jirayucharoensak , Peter A. Beerel An asynchronous pipeline comparisons with application to DCT matrix-vector multiplication. [Citation Graph (0, 0)][DBLP ] ISCAS (5), 2003, pp:361-364 [Conf ] Peter A. Beerel , Cheng-Ta Hsieh , Suhrid A. Wadekar Estimation of energy consumption in speed-independent control circuits. [Citation Graph (0, 0)][DBLP ] ISLPD, 1995, pp:39-44 [Conf ] Peter A. Beerel , Sangyun Kim , Pei-Chuan Yeh , Kyeounsoo Kim Statistically optimized asynchronous barrel shifters for variable length codecs. [Citation Graph (0, 0)][DBLP ] ISLPED, 1999, pp:261-263 [Conf ] Kyeounsoo Kim , Peter A. Beerel , Youpyo Hong An asynchronous matrix-vector multiplier for discrete cosine transform. [Citation Graph (0, 0)][DBLP ] ISLPED, 2000, pp:256-261 [Conf ] Joong-Seok Moon , William C. Athas , Peter A. Beerel Theory and practical implementation of harmonic resonant rail driver. [Citation Graph (0, 0)][DBLP ] ISLPED, 2001, pp:153-158 [Conf ] Peter A. Beerel Asynchronous Circuits: An Increasingly Practical Design Solution (invited). [Citation Graph (0, 0)][DBLP ] ISQED, 2002, pp:367-372 [Conf ] Pankaj Golani , Peter A. Beerel High-Performance Noise-Robust Asynchronous Circuits. [Citation Graph (0, 0)][DBLP ] ISVLSI, 2006, pp:173-178 [Conf ] Peter A. Beerel Asynchronous Design for High-Speed and Low-Power Circuits. [Citation Graph (0, 0)][DBLP ] PATMOS, 2006, pp:669- [Conf ] Pankaj Golani , Peter A. Beerel Back Annotation in High Speed Asynchronous Design. [Citation Graph (0, 0)][DBLP ] PATMOS, 2005, pp:227-236 [Conf ] Sangyun Kim , Sunan Tugsinavisut , Peter A. Beerel Reducing probabilistic timed petri nets for asynchronous architectural analysis. [Citation Graph (0, 0)][DBLP ] Timing Issues in the Specification and Synthesis of Digital Systems, 2002, pp:140-147 [Conf ] Peter A. Beerel , Jordi Cortadella , Alex Kondratyev Bridging the Gap between Asynchronous Design and Designers. [Citation Graph (0, 0)][DBLP ] VLSI Design, 2004, pp:18-20 [Conf ] Peter A. Beerel , Jerry R. Burch , Teresa H. Y. Meng Checking Combinational Equivalence of Speed-Independent Circuits. [Citation Graph (0, 0)][DBLP ] Formal Methods in System Design, 1998, v:13, n:1, pp:37-85 [Journal ] Vida Vakilotojar , Peter A. Beerel RTL verification of timed asynchronous and heterogeneous systems using symbolic model checking. [Citation Graph (0, 0)][DBLP ] Integration, 1997, v:24, n:1, pp:19-35 [Journal ] Peter A. Beerel , Cheng-Ta Hsieh , Suhrid A. Wadekar Estimation of energy consumption in speed-independent control circuits. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:6, pp:672-680 [Journal ] Peter A. Beerel , Chris J. Myers , Teresa H. Y. Meng Covering conditions and algorithms for the synthesis of speed-independent circuits. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:3, pp:205-219 [Journal ] Wei-Chun Chou , Peter A. Beerel , Kenneth Y. Yun Average-case technology mapping of asynchronous burst-mode circuits. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:10, pp:1418-1434 [Journal ] Youpyo Hong , Peter A. Beerel , Jerry R. Burch , Kenneth L. McMillan Sibling-substitution-based BDD minimization using don't cares. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:1, pp:44-55 [Journal ] Sangyun Kim , Peter A. Beerel Pipeline optimization for asynchronous circuits: complexity analysis and an efficient optimal algorithm. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:3, pp:389-402 [Journal ] Aiguo Xie , Peter A. Beerel Implicit enumeration of strongly connected components and anapplication to formal verification. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:10, pp:1225-1230 [Journal ] Aiguo Xie , Peter A. Beerel Efficient state classification of finite-state Markov chains. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:12, pp:1334-1339 [Journal ] Aiguo Xie , Peter A. Beerel Accelerating Markovian analysis of asynchronous systems using state compression. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:7, pp:869-888 [Journal ] Sunan Tugsinavisut , Youpyo Hong , Daewook Kim , Kyeounsoo Kim , Peter A. Beerel Efficient asynchronous bundled-data pipelines for DCT matrix-vector multiplication. [Citation Graph (0, 0)][DBLP ] IEEE Trans. VLSI Syst., 2005, v:13, n:4, pp:448-461 [Journal ] Recep O. Ozdag , Peter A. Beerel An Asynchronous Low-Power High-Performance Sequential Decoder Implemented With QDI Templates. [Citation Graph (0, 0)][DBLP ] IEEE Trans. VLSI Syst., 2006, v:14, n:9, pp:975-985 [Journal ] Kenneth Y. Yun , Peter A. Beerel , Vida Vakilotojar , Ayoob E. Dooply , Julio Arceo The design and verification of a high-performance low-control-overhead asynchronous differential equation solver. [Citation Graph (0, 0)][DBLP ] IEEE Trans. VLSI Syst., 1998, v:6, n:4, pp:643-655 [Journal ] Joong-Seok Moon , William C. Athas , Sigfrid D. Soli , Jeffrey T. Draper , Peter A. Beerel Voltage-pulse driven harmonic resonant rail drivers for low-power applications. [Citation Graph (0, 0)][DBLP ] IEEE Trans. VLSI Syst., 2003, v:11, n:5, pp:762-777 [Journal ] Pankaj Golani , Peter A. Beerel Back-Annotation in High-Speed Asynchronous Design. [Citation Graph (0, 0)][DBLP ] J. Low Power Electronics, 2006, v:2, n:1, pp:37-44 [Journal ] Timing Verification of GasP Asynchronous Circuits: Predicted Delay Variations Observed by Experiment. [Citation Graph (, )][DBLP ] Crosstalk in High-Performance Asynchronous Designs. [Citation Graph (, )][DBLP ] High Level Modeling of Channel-Based Asynchronous Circuits Using Verilog. [Citation Graph (, )][DBLP ] Search in 0.007secs, Finished in 0.420secs