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Christian Landrault: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch
    A Gated Clock Scheme for Low Power Scan Testing of Logic ICs or Embedded Cores. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2001, pp:253-258 [Conf]
  2. Christophe Fagot, Olivier Gascuel, Patrick Girard, Christian Landrault
    A Ring Architecture Strategy for BIST Test Pattern Generation. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1998, pp:418-423 [Conf]
  3. Marie-Lise Flottes, Christian Landrault, A. Petitqueux
    Design for sequential testability: an internal state reseeding approach for 100 % fault coverage. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2000, pp:404-0 [Conf]
  4. Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch
    An adjacency-based test pattern generator for low power BIST design. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2000, pp:459-464 [Conf]
  5. Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch
    Circuit Partitioning for Low Power BIST Design with Minimized Peak Power Consumption. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1999, pp:89-94 [Conf]
  6. Patrick Girard, Christian Landrault, V. Moreda, Serge Pravossoudovitch, Arnaud Virazel
    A BIST Structure to Test Delay Faults in a Scan Environment. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1998, pp:435-439 [Conf]
  7. S. Lavabre, Yves Bertrand, Michel Renovell, Christian Landrault
    Test configurations to enhance the testability of sequential circuits. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1995, pp:160-168 [Conf]
  8. Marc Perbost, Ludovic Le Lan, Christian Landrault
    Automatic Testability Analysis of Boards and MCMs at Chip Level. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1997, pp:36-41 [Conf]
  9. Patrick Girard, Christian Landrault, Serge Pravossoudovitch
    A Novel Approach to Delay-Fault Diagnosis. [Citation Graph (0, 0)][DBLP]
    DAC, 1992, pp:357-360 [Conf]
  10. Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
    Design of Routing-Constrained Low Power Scan Chains. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:62-67 [Conf]
  11. A. Toulouse, David Bernard, Christian Landrault, Pascal Nouet
    Efficient 3D Modelling for Extraction of Interconnect Capacitances in Deep Submicron Dense Layouts. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:576-580 [Conf]
  12. Alexandre Rousset, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
    A Mixed Approach for Unified Logic Diagnosis. [Citation Graph (0, 0)][DBLP]
    DDECS, 2007, pp:239-242 [Conf]
  13. Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
    Design of Routing-Constrained Low Power Scan Chains. [Citation Graph (0, 0)][DBLP]
    DELTA, 2004, pp:287-294 [Conf]
  14. Yannick Bonhomme, Patrick Girard, Christian Landrault, Serge Pravossoudovitch
    Test Power: a Big Issue in Large SOC Designs. [Citation Graph (0, 0)][DBLP]
    DELTA, 2002, pp:447-449 [Conf]
  15. D. Dumas, Patrick Girard, Christian Landrault, Serge Pravossoudovitch
    Effectiveness of a Variable Sampling Time Strategy for Delay Fault Diagnosis. [Citation Graph (0, 0)][DBLP]
    EDAC-ETC-EUROASIC, 1994, pp:518-523 [Conf]
  16. Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch
    A Test Vector Ordering Technique for Switching Activity Reduction During Test Operation. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1999, pp:24-0 [Conf]
  17. David Bernard, Christian Landrault, Pascal Nouet
    Interconnect Capacitance Modelling in a VDSM CMOS Technology. [Citation Graph (0, 0)][DBLP]
    VLSI-SOC, 2001, pp:133-144 [Conf]
  18. René David, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
    Random Adjacent Sequences: An Efficient Solution for Logic BIST. [Citation Graph (0, 0)][DBLP]
    VLSI-SOC, 2001, pp:413-424 [Conf]
  19. Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
    Comparison between Random and Pseudo-Random Generation for BIST of Delay, Stuck-at and Bridging Faults. [Citation Graph (0, 0)][DBLP]
    IOLTW, 2000, pp:121-126 [Conf]
  20. Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch
    A Gated Clock Scheme for Low Power Scan-Based BIST. [Citation Graph (0, 0)][DBLP]
    IOLTW, 2001, pp:87-89 [Conf]
  21. Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, J. Figueras, S. Manich, P. Teixeira, M. Santos
    Low-energy BIST design: impact of the LFSR TPG parameters on the weighted switching activity. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 1999, pp:110-113 [Conf]
  22. Patrick Girard, Christian Landrault, Serge Pravossoudovitch, D. Severac
    A gate resizing technique for high reduction in power consumption. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1997, pp:281-286 [Conf]
  23. Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch
    Efficient Scan Chain Design for Power Minimization During Scan Testing Under Routing Constraint. [Citation Graph (0, 0)][DBLP]
    ITC, 2003, pp:488-493 [Conf]
  24. Yannick Bonhomme, Patrick Girard, Christian Landrault, Serge Pravossoudovitch
    Power Driven Chaining of Flip-Flops in Scan Architectures. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:796-803 [Conf]
  25. D. Dumas, Patrick Girard, Christian Landrault, Serge Pravossoudovitch
    An Implicit Delay-Fault Simulation Method with Approximate Detection Threshold Calculation. [Citation Graph (0, 0)][DBLP]
    ITC, 1993, pp:705-713 [Conf]
  26. Christophe Fagot, Patrick Girard, Christian Landrault
    On Using Machine Learning for Logic BIST. [Citation Graph (0, 0)][DBLP]
    ITC, 1997, pp:338-346 [Conf]
  27. Patrick Girard, Christian Landrault, Loïs Guiller, Serge Pravossoudovitch
    Low power BIST design by hypergraph partitioning: methodology and architectures. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:652-661 [Conf]
  28. Patrick Girard, Christian Landrault, Serge Pravossoudovitch, B. Rodriguez
    A Diagnostic ATPG for Delay Faults Based on Genetic Algorithms. [Citation Graph (0, 0)][DBLP]
    ITC, 1996, pp:286-293 [Conf]
  29. Christian Landrault, Marie-Lise Flottes, Bruno Rouzeyre
    Is High-Level Test Synthesis Just Design for Test? [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:294- [Conf]
  30. Christian Landrault, Jean-Claude Laprie
    SURF - A Program for Modeling and Reliability Prediction for Fault-Tolerant Computing Systems. [Citation Graph (0, 0)][DBLP]
    Jerusalem Conference on Information Technology, 1978, pp:17-26 [Conf]
  31. Nabil Badereddine, Patrick Girard, Arnaud Virazel, Serge Pravossoudovitch, Christian Landrault
    Controlling Peak Power Consumption During Scan Testing: Power-Aware DfT and Test Set Perspectives. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2005, pp:540-549 [Conf]
  32. J. Abraham, P. Frankl, Christian Landrault, Meryem Marzouki, Paolo Prinetto, Chantal Robach, Pascale Thévenod-Fosse
    Hardware Test: Can We Learn from Software Testing? [Citation Graph (0, 0)][DBLP]
    VTS, 1997, pp:320-321 [Conf]
  33. Laurent Bréhélin, Olivier Gascuel, Gilles Caraux, Patrick Girard, Christian Landrault
    Hidden Markov and Independence Models with Patterns for Sequential BIST. [Citation Graph (0, 0)][DBLP]
    VTS, 2000, pp:359-368 [Conf]
  34. O. Ginez, Jean Michel Daga, Marylene Combe, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
    An Overview of Failure Mechanisms in Embedded Flash Memories. [Citation Graph (0, 0)][DBLP]
    VTS, 2006, pp:108-113 [Conf]
  35. Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch
    A Test Vector Inhibiting Technique for Low Energy BIST Design. [Citation Graph (0, 0)][DBLP]
    VTS, 1999, pp:407-412 [Conf]
  36. Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Hans-Joachim Wunderlich
    A Modified Clock Scheme for a Low Power BIST Test Pattern Generator. [Citation Graph (0, 0)][DBLP]
    VTS, 2001, pp:306-311 [Conf]
  37. Patrick Girard, Christian Landrault, V. Moreda, Serge Pravossoudovitch
    An optimized BIST test pattern generator for delay testing. [Citation Graph (0, 0)][DBLP]
    VTS, 1997, pp:94-100 [Conf]
  38. Patrick Girard, Christian Landrault, Serge Pravossoudovitch, B. Rodriguez
    Diagnostic of path and gate delay faults in non-scan sequential circuits. [Citation Graph (0, 0)][DBLP]
    VTS, 1995, pp:380-386 [Conf]
  39. S. Cremoux, Christophe Fagot, Patrick Girard, Christian Landrault, Serge Pravossoudovitch
    A new test pattern generation method for delay fault testing. [Citation Graph (0, 0)][DBLP]
    VTS, 1996, pp:296-301 [Conf]
  40. René David, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
    On Using Efficient Test Sequences for BIST. [Citation Graph (0, 0)][DBLP]
    VTS, 2002, pp:145-152 [Conf]
  41. O. Ginez, Jean Michel Daga, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
    Retention and Reliability Problems in Embedded Flash Memories: Analysis and Test of Defective 2T-FLOTOX Tunnel Window. [Citation Graph (0, 0)][DBLP]
    VTS, 2007, pp:47-52 [Conf]
  42. A. Ney, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian
    Un-Restored Destructive Write Faults Due to Resistive-Open Defects in the Write Driver of SRAMs. [Citation Graph (0, 0)][DBLP]
    VTS, 2007, pp:361-368 [Conf]
  43. Patrick Girard, Christian Landrault, Serge Pravossoudovitch
    Delay-Fault Diagnosis by Critical-Path Tracing. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1992, v:9, n:4, pp:27-32 [Journal]
  44. Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel, Hans-Joachim Wunderlich
    High Defect Coverage with Low-Power Test Sequences in a BIST Environment. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2002, v:19, n:5, pp:44-52 [Journal]
  45. Patrick Girard, Christian Landrault, Serge Pravossoudovitch, D. Severac
    A non-iterative gate resizing algorithm for high reduction in power consumption. [Citation Graph (0, 0)][DBLP]
    Integration, 1997, v:24, n:1, pp:37-52 [Journal]
  46. Alain Costes, Christian Landrault, Jean-Claude Laprie
    Reliability and Availability Models for Maintained Systems Featuring Hardware Failures and Design Faults. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1978, v:27, n:6, pp:548-560 [Journal]
  47. Yves Crouzet, Christian Landrault
    Design of Self-Checking MOS-LSI Circuits: Application to a Four-Bit Microprocessor. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1980, v:29, n:6, pp:532-537 [Journal]
  48. A. Ney, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian
    Slow write driver faults in 65nm SRAM technology: analysis and March test solution. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:528-533 [Conf]
  49. Nabil Badereddine, Patrick Girard, Serge Pravossoudovitch, Christian Landrault, Arnaud Virazel, Hans-Joachim Wunderlich
    Structural-Based Power-Aware Assignment of Don't Cares for Peak Power Reduction during Scan Testing. [Citation Graph (0, 0)][DBLP]
    VLSI-SoC, 2006, pp:403-408 [Conf]
  50. Nabil Badereddine, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Christian Landrault
    Scan Cell Reordering for Peak Power Reduction during Scan Test Cycles. [Citation Graph (0, 0)][DBLP]
    VLSI-SoC, 2005, pp:267-281 [Conf]
  51. Alexandre Rousset, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
    DERRIC: A Tool for Unified Logic Diagnosis. [Citation Graph (0, 0)][DBLP]
    European Test Symposium, 2007, pp:13-20 [Conf]
  52. O. Ginez, Jean Michel Daga, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
    Electrical Simulation Model of the 2T-FLOTOX Core-Cell for Defect Injection and Faulty Behavior Prediction in eFlash Memories. [Citation Graph (0, 0)][DBLP]
    European Test Symposium, 2007, pp:77-84 [Conf]
  53. A. Ney, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian
    Dynamic Two-Cell Incorrect Read Fault Due to Resistive-Open Defects in the Sense Amplifiers of SRAMs. [Citation Graph (0, 0)][DBLP]
    European Test Symposium, 2007, pp:97-104 [Conf]
  54. Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
    A Gated Clock Scheme for Low Power Testing of Logic Cores. [Citation Graph (0, 0)][DBLP]
    J. Electronic Testing, 2006, v:22, n:1, pp:89-99 [Journal]

  55. Improving Diagnosis Resolution without Physical Information. [Citation Graph (, )][DBLP]


  56. Using TMR Architectures for Yield Improvement. [Citation Graph (, )][DBLP]


  57. Fault modelling and fault equivalence in CMOS technology. [Citation Graph (, )][DBLP]


  58. Yield Improvement, Fault-Tolerance to the Rescue?. [Citation Graph (, )][DBLP]


  59. Something I Always Wanted to Know About Test, But Was Afraid to Ask. [Citation Graph (, )][DBLP]


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