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Conferences in DBLP
- Parag K. Lala, B. Kiran Kumar
An Architecture for Self-Healing Digital Systems. [Citation Graph (0, 0)][DBLP]
IOLTW, 2002, pp:3-7 [Conf]
- Daniele Rossi, V. E. S. van Dijk, Richard P. Kleihorst, A. H. Nieuwland, Cecilia Metra
Coding Scheme for Low Energy Consumption Fault-Tolerant Bus. [Citation Graph (0, 0)][DBLP]
IOLTW, 2002, pp:8-12 [Conf]
- A. Matrosova, V. Andreeva, Yu. Sedov
Survivable Discrete Circuits Design. [Citation Graph (0, 0)][DBLP]
IOLTW, 2002, pp:13-0 [Conf]
- Astrit Ademaj, Petr Grillinger, Pavel Herout, Jan Hlavicka
Fault Tolerance Evaluation Using Two Software Based Fault Injection Methods. [Citation Graph (0, 0)][DBLP]
IOLTW, 2002, pp:21-25 [Conf]
- Silvia Chiusano, Stefano Di Carlo, Paolo Prinetto
Automated Synthesis of SEU Tolerant Architectures from OO Descriptions. [Citation Graph (0, 0)][DBLP]
IOLTW, 2002, pp:26-31 [Conf]
- Cristiana Bolchini, Luigi Pomante, Fabio Salice, Donatella Sciuto
A System Level Approach in Designing Dual-Duplex Fault Tolerant Embedded Systems. [Citation Graph (0, 0)][DBLP]
IOLTW, 2002, pp:32-0 [Conf]
- Daniel Marienfeld, Egor S. Sogomonyan, Vitalij Ocheretnij, Michael Gössel
A New Self-Checking Code-Disjoint Carry-Skip Adder. [Citation Graph (0, 0)][DBLP]
IOLTW, 2002, pp:39-43 [Conf]
- Ilya Levin, Vladimir Sinelnikov, Mark G. Karpovsky, Sergey Ostanin
Sequential Circuits Applicable for Detecting Different Types of Faults. [Citation Graph (0, 0)][DBLP]
IOLTW, 2002, pp:44-0 [Conf]
- Amine M'sir, Fabrice Monteiro, Abbas Dandache, Bernard Lepley
A High Speed Encoder for Recursive Systematic Convolutive Codes. [Citation Graph (0, 0)][DBLP]
IOLTW, 2002, pp:51-55 [Conf]
- Y. Tsiatouhas, Angela Arapoyanni, Dimitris Nikolos, Th. Haniotakis
A Hierarchical Architecture for Concurrent Soft Error Detection Based on Current Sensing. [Citation Graph (0, 0)][DBLP]
IOLTW, 2002, pp:56-60 [Conf]
- Huy Nguyen, Abhijit Chatterjee
Design of Real-Number Checksum Codes Using Shared Partial Computation for CED in Linear DSP Systems. [Citation Graph (0, 0)][DBLP]
IOLTW, 2002, pp:61-0 [Conf]
- Matthias Pflanz, K. Walther, Christian Galke, Heinrich Theodor Vierhaus
On-Line Error Detection and Correction in Storage Elements with Cross-Parity Check. [Citation Graph (0, 0)][DBLP]
IOLTW, 2002, pp:69-73 [Conf]
- Feng Gao, John P. Hayes
On-Line Monitor Design of Finite-State Machines. [Citation Graph (0, 0)][DBLP]
IOLTW, 2002, pp:74-78 [Conf]
- Marcelo Negreiros, Luigi Carro, Altamiro Amadeu Susin
A Statistical Sampler for a New On-line Analog Test Method. [Citation Graph (0, 0)][DBLP]
IOLTW, 2002, pp:79-0 [Conf]
- Joan Font, J. Ginard, Eugeni Isern, Miquel Roca, Jaume Segura, Eugenio García
A BICS for CMOS Opamps by Monitoring the Supply Current Peak. [Citation Graph (0, 0)][DBLP]
IOLTW, 2002, pp:94-98 [Conf]
- Rosa Rodríguez-Montañés, D. Muñoz, L. Balado, Joan Figueras
Analog Switches in Programmable Analog Devices: Quiescent Defective Behaviours. [Citation Graph (0, 0)][DBLP]
IOLTW, 2002, pp:99-103 [Conf]
- Régis Leveugle, K. Hadjiat
Multi-Level Fault Injection Experiments Based on VHDL Descriptions: A Case Study. [Citation Graph (0, 0)][DBLP]
IOLTW, 2002, pp:107-111 [Conf]
- Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante
Analysis of SEU Effects in a Pipelined Processor. [Citation Graph (0, 0)][DBLP]
IOLTW, 2002, pp:112-116 [Conf]
- Gian-Carlo Cardarilli, F. Kaddour, A. Leandri, Marco Ottavi, Salvatore Pontarelli, Raoul Velazco
Bit Flip Injection in Processor-Based Architectures: A Case Study. [Citation Graph (0, 0)][DBLP]
IOLTW, 2002, pp:117-0 [Conf]
- Miron Abramovici, Charles E. Stroud
BIST-Based Delay-Fault Testing in FPGAs. [Citation Graph (0, 0)][DBLP]
IOLTW, 2002, pp:131-134 [Conf]
- N. Axelos, J. Watson, D. Taylor, A. Platts
Built-In-Self-Test of Analogue Circuits Using Optimised Fault Sets and Transient Response Testing. [Citation Graph (0, 0)][DBLP]
IOLTW, 2002, pp:135-139 [Conf]
- Nadir Z. Basturkmen, Sudhakar M. Reddy, Irith Pomeranz
A Low Power Pseudo-Random BIST Technique. [Citation Graph (0, 0)][DBLP]
IOLTW, 2002, pp:140-0 [Conf]
- Ilia Polian, Bernd Becker
Stop & Go BIST. [Citation Graph (0, 0)][DBLP]
IOLTW, 2002, pp:147-151 [Conf]
- Giorgos Dimitrakopoulos, Dimitris Nikolos, Dimitris Bakalis
Bit-Serial Test Pattern Generation by an Accumulator Behaving as a Non-Linear Feedback Shift Register. [Citation Graph (0, 0)][DBLP]
IOLTW, 2002, pp:152-157 [Conf]
- Dimitri Kagaris
Built-in Generation of m -Sequences with Irreducible Characteristic Polynomials. [Citation Graph (0, 0)][DBLP]
IOLTW, 2002, pp:158-0 [Conf]
- Manuel G. Gericota, Gustavo R. Alves, Miguel L. Silva, José M. Ferreira
Active Replication: Towards a Truly SRAM-Based FPGA On-Line Concurrent Testing. [Citation Graph (0, 0)][DBLP]
IOLTW, 2002, pp:165-169 [Conf]
- Giuseppe Di Gregorio, Maria Grazia La Rosa, Biagio Russo
Checkers for RF Matching Networks on an Automatic Test Board. [Citation Graph (0, 0)][DBLP]
IOLTW, 2002, pp:170-0 [Conf]
- Carlo Dallavalle
Adaptive IDDQ: How to Set an IDDQ Limit for any Device Under Test. [Citation Graph (0, 0)][DBLP]
IOLTW, 2002, pp:177- [Conf]
- Christian Galke, Matthias Pflanz, Heinrich Theodor Vierhaus
On-line Detection and Compensation of Transient Errors in Processor Pipeline-Structures. [Citation Graph (0, 0)][DBLP]
IOLTW, 2002, pp:178- [Conf]
- Jose Miguel Vieira dos Santos
Recovering Sequential Circuits from Temporary Faults: The Survival Capability of Scan-Cells. [Citation Graph (0, 0)][DBLP]
IOLTW, 2002, pp:179- [Conf]
- Naotake Kamiura, Kazuharu Yamato, Teijiro Isokawa, Nobuyuki Matsui
Learning-Based On-Line Testing in Feedforward Neural Networks. [Citation Graph (0, 0)][DBLP]
IOLTW, 2002, pp:180- [Conf]
- Adam Kristof
On-Line Detection of Short Circuits in Digital Devices and Systems. [Citation Graph (0, 0)][DBLP]
IOLTW, 2002, pp:183- [Conf]
- Mohammad A. Naal, M. Rakotoar, Emmanuel Simeu, Chouki Aktouf
Using Concurrent and Semi-Concurrent On-Line Testing During HLS: An Adaptable Approach. [Citation Graph (0, 0)][DBLP]
IOLTW, 2002, pp:184- [Conf]
- Petros Oikonomakos, Mark Zwolinski
Transformation Based Insertion of On-Line Testing Resources in a High-Level Synthesis Environment. [Citation Graph (0, 0)][DBLP]
IOLTW, 2002, pp:185- [Conf]
- Aleksandra Rankov, Gaynor E. Taylor, John Webster
Robust Data Compression for Analogue Test Outputs. [Citation Graph (0, 0)][DBLP]
IOLTW, 2002, pp:186- [Conf]
- Fabian Vargas, Rubem Dutra R. Fagundes, Daniel Barros Jr.
A New On-Line Robust Approach to Design Noise Immune Speech Recognition Systems. [Citation Graph (0, 0)][DBLP]
IOLTW, 2002, pp:187- [Conf]
- Ari Virtanen
Radiation Effects Facility RADEF. [Citation Graph (0, 0)][DBLP]
IOLTW, 2002, pp:188- [Conf]
- Ilia Polian, Martin Keim, Nicolai Mallig, Bernd Becker
Sequential n -Detection Criteria: Keep It Simple. [Citation Graph (0, 0)][DBLP]
IOLTW, 2002, pp:189- [Conf]
- Chouki Aktouf, Benoît Pannetier, Pierre Lemaître-Auger, Smail Tedjini
On-line Testing of Embedded Systems Using Optical Probes: System Modeling and Probing Technology. [Citation Graph (0, 0)][DBLP]
IOLTW, 2002, pp:191- [Conf]
- B. Alorda, André Ivanov, Jaume Segura
An Off-Chip Sensor Circuit for On-Line Transient Current Testing. [Citation Graph (0, 0)][DBLP]
IOLTW, 2002, pp:192- [Conf]
- Luis Berrojo, Isabel González, Luis Entrena, Celia López, Fulvio Corno, Matteo Sonza Reorda, Giovanni Squillero
Analysis of the Equivalences and Dominances of Transient Faults at the RT Level. [Citation Graph (0, 0)][DBLP]
IOLTW, 2002, pp:193- [Conf]
- Fernanda Gusmão de Lima, Luigi Carro, Raoul Velazco, Ricardo Augusto da Luz Reis
Injecting Multiple Upsets in a SEU Tolerant 8051 Micro-Controller. [Citation Graph (0, 0)][DBLP]
IOLTW, 2002, pp:194- [Conf]
- F. Kaddour, S. Rezgui, Raoul Velazco, S. Rodriguez, J. R. De Mingo
Error Rate Estimation for a Flight Application Using the CEU Fault Injection Approach. [Citation Graph (0, 0)][DBLP]
IOLTW, 2002, pp:195- [Conf]
- Alvin Jee
Defect-Oriented Analysis of Memory BIST Tests. [Citation Graph (0, 0)][DBLP]
IOLTW, 2002, pp:201-205 [Conf]
- Davide Appello, Alessandra Fudoli, Vincenzo Tancorre, Fulvio Corno, Maurizio Rebaudengo, Matteo Sonza Reorda
A BIST-Based Solution for the Diagnosis of Embedded Memories Adopting Image Processing Techniques. [Citation Graph (0, 0)][DBLP]
IOLTW, 2002, pp:206-210 [Conf]
- Farzin Karimi, Fabrizio Lombardi
A Scan-Bist Environment for Testing Embedded Memories. [Citation Graph (0, 0)][DBLP]
IOLTW, 2002, pp:211-0 [Conf]
- Daniele Rossi, Cecilia Metra, Bruno Riccò
Fast and Compact Error Correcting Scheme for Reliable Multilevel Flash Memories. [Citation Graph (0, 0)][DBLP]
IOLTW, 2002, pp:221-225 [Conf]
- Bernard Coloma, Patrick Delaunay, Olivier Husson
High Speed 15 ns 4 Mbits SRAM for Space Application. [Citation Graph (0, 0)][DBLP]
IOLTW, 2002, pp:226-0 [Conf]
- D. Bied-Charreton, D. Guillon, B. Jacques
The YATE Fail-Safe Interface: The User's Point of View. [Citation Graph (0, 0)][DBLP]
IOLTW, 2002, pp:233-0 [Conf]
- Alberto Manzone, Diego De Costantini
Fault Tolerant Insertion and Verification: A Case Study. [Citation Graph (0, 0)][DBLP]
IOLTW, 2002, pp:238-242 [Conf]
- Luca Schiano, Cecilia Metra, Diego Marino
Design and Implementation of a Self-Checking Scheme for Railway Trackside Systems. [Citation Graph (0, 0)][DBLP]
IOLTW, 2002, pp:243-0 [Conf]
- Emmanuel Rondey, Yann Tellier, Simone Borri
A Silicon-Based Yiel Gain Evaluation Methodology for Embedded-SRAMs with Different Redundancy Scenarios. [Citation Graph (0, 0)][DBLP]
IOLTW, 2002, pp:251-255 [Conf]
- Valery A. Vardanian, Yervant Zorian
A March-Based Fault Location Algorithm for Static Random Access Memories. [Citation Graph (0, 0)][DBLP]
IOLTW, 2002, pp:256-261 [Conf]
- Rei-Fu Huang, Jin-Fu Li, Jen-Chieh Yeh, Cheng-Wen Wu
A Simulator for E aluating Redundancy Analysis Algorithms of Repairable Embedded Memories. [Citation Graph (0, 0)][DBLP]
IOLTW, 2002, pp:262-0 [Conf]
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