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## Search the dblp DataBase
Keshab K. Parhi:
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## Publications of Author- Vijay Sundararajan, Keshab K. Parhi
**Low Power Gate Resizing of Combinational Circuits by Buffer-Redistribution.**[Citation Graph (0, 0)][DBLP] ARVLSI, 1999, pp:170-185 [Conf] - William L. Freking, Keshab K. Parhi
**Performance-Scalable Array Architectures for Modular Multiplication.**[Citation Graph (0, 0)][DBLP] ASAP, 2000, pp:149-0 [Conf] - Lijun Gao, Keshab K. Parhi
**Block-Update Parallel Processing QRD-RLS Algorithm for Throughput Improvement with Low Power Consumption.**[Citation Graph (0, 0)][DBLP] ASAP, 2000, pp:225-234 [Conf] - Daesun Oh, Keshab K. Parhi
**Low Complexity Design of High Speed Parallel Decision Feedback Equalizers.**[Citation Graph (0, 0)][DBLP] ASAP, 2006, pp:118-124 [Conf] - David A. Parker, Keshab K. Parhi
**Area-Efficient Parallel FIR Digital Filter Implementations.**[Citation Graph (0, 0)][DBLP] ASAP, 1996, pp:93-111 [Conf] - Leilei Song, Keshab K. Parhi
**Efficient Finite Field Serial/Parallel Multiplication.**[Citation Graph (0, 0)][DBLP] ASAP, 1996, pp:72-0 [Conf] - Vijay Sundararajan, Keshab K. Parhi
**Synthesis of low power folded programmable coefficient FIR digital filters (short paper).**[Citation Graph (0, 0)][DBLP] ASP-DAC, 2000, pp:153-156 [Conf] - Vijay Sundararajan, Keshab K. Parhi
**Data transmission over a bus with peak-limited transition activity.**[Citation Graph (0, 0)][DBLP] ASP-DAC, 2000, pp:221-224 [Conf] - Janardhan H. Satyanarayana, Keshab K. Parhi
**HEAT: Hierarchical Energy Analysis Tool.**[Citation Graph (0, 0)][DBLP] DAC, 1996, pp:9-14 [Conf] - Vijay Sundararajan, Keshab K. Parhi
**Synthesis of Low Power CMOS VLSI Circuits Using Dual Supply Voltages.**[Citation Graph (0, 0)][DBLP] DAC, 1999, pp:72-75 [Conf] - Vijay Sundararajan, Sachin S. Sapatnekar, Keshab K. Parhi
**MINFLOTRANSIT: min-cost flow based transistor sizing tool.**[Citation Graph (0, 0)][DBLP] DAC, 2000, pp:649-664 [Conf] - Yanni Chen, Keshab K. Parhi
**High throughput overlapped message passing for low density parity check codes.**[Citation Graph (0, 0)][DBLP] ACM Great Lakes Symposium on VLSI, 2003, pp:245-248 [Conf] - Yun-Nan Chang, Ching-Yi Wang, Keshab K. Parhi
**Loop-List Scheduling for Heterogeneous Functional Units.**[Citation Graph (0, 0)][DBLP] Great Lakes Symposium on VLSI, 1996, pp:2-7 [Conf] - Lijun Gao, Keshab K. Parhi
**Models for power consumption and power grid noise due to datapath transition activity.**[Citation Graph (0, 0)][DBLP] ACM Great Lakes Symposium on VLSI, 2001, pp:121-126 [Conf] - Bibhudatta Sahoo, Martin Kuhlmann, Keshab K. Parhi
**A low-power correlator.**[Citation Graph (0, 0)][DBLP] ACM Great Lakes Symposium on VLSI, 2000, pp:153-155 [Conf] - Janardhan H. Satyanarayana, Keshab K. Parhi
**Theoretical Analysis of Word-Level Switching Activity in the Presence of Glitching and Correlation.**[Citation Graph (0, 0)][DBLP] Great Lakes Symposium on VLSI, 1999, pp:46-49 [Conf] - Vijay Sundararajan, Keshab K. Parhi
**Reducing bus transition activity by limited weight coding with codeword slimming.**[Citation Graph (0, 0)][DBLP] ACM Great Lakes Symposium on VLSI, 2000, pp:13-16 [Conf] - Tong Zhang, Keshab K. Parhi
**On the high-speed VLSI implementation of errors-and-erasures correcting reed-solomon decoders.**[Citation Graph (0, 0)][DBLP] ACM Great Lakes Symposium on VLSI, 2002, pp:89-93 [Conf] - Xinmiao Zhang, Keshab K. Parhi
**High-speed architectures for parallel long BCH encoders.**[Citation Graph (0, 0)][DBLP] ACM Great Lakes Symposium on VLSI, 2004, pp:1-6 [Conf] - Kazuhito Ito, Lori E. Lucke, Keshab K. Parhi
**Module selection and data format conversion for cost-optimal DSP synthesis.**[Citation Graph (0, 0)][DBLP] ICCAD, 1994, pp:322-329 [Conf] - Vijay Sundararajan, Sachin S. Sapatnekar, Keshab K. Parhi
**Marsh: min-area retiming with setup and hold constraints.**[Citation Graph (0, 0)][DBLP] ICCAD, 1999, pp:2-6 [Conf] - Yun-Nan Chang, Janardhan H. Satyanarayana, Keshab K. Parhi
**Design and Implementation of Low-Power Digit-Serial Multipliers.**[Citation Graph (0, 0)][DBLP] ICCD, 1997, pp:186-195 [Conf] - William L. Freking, Keshab K. Parhi
**A Unified Method for Iterative Computation of Modular Multiplication and Reduction Operations.**[Citation Graph (0, 0)][DBLP] ICCD, 1999, pp:80-0 [Conf] - Martin Kuhlmann, Sachin S. Sapatnekar, Keshab K. Parhi
**Efficient Crosstalk Estimation.**[Citation Graph (0, 0)][DBLP] ICCD, 1999, pp:266-0 [Conf] - Keshab K. Parhi
**Fast Low-Energy VLSI Binary Addition.**[Citation Graph (0, 0)][DBLP] ICCD, 1997, pp:676-684 [Conf] - Janardhan H. Satyanarayana, Keshab K. Parhi, Leilei Song, Yun-Nan Chang
**Systematic analysis of bounds on power consumption in pipelined and non-pipelined multipliers.**[Citation Graph (0, 0)][DBLP] ICCD, 1996, pp:492-499 [Conf] - Hosahalli R. Srinivas, Keshab K. Parhi
**High-Speed VLSI Arithmetic Processor Architectures Using Hybrid Number Representation.**[Citation Graph (0, 0)][DBLP] ICCD, 1991, pp:564-571 [Conf] - Hosahalli R. Srinivas, Keshab K. Parhi
**A floating point radix 2 shared division/square root chip.**[Citation Graph (0, 0)][DBLP] ICCD, 1995, pp:472-478 [Conf] - Hosahalli R. Srinivas, Bapiraju Vinnakota, Keshab K. Parhi
**A C-Testable Carry-Free Divider.**[Citation Graph (0, 0)][DBLP] ICCD, 1993, pp:206-213 [Conf] - Michael E. Zervakis, Vijay Sundararajan, Keshab K. Parhi
**A Wavelet-Domain Algorithm for Denoising in the Presence of Noise Outliers.**[Citation Graph (0, 0)][DBLP] ICIP (1), 1997, pp:632-635 [Conf] - Keshab K. Parhi, David G. Messerschmitt
**Fully-Static Rate-Optimal Scheduling of Iterative Data-Flow Programs via Optimum Unfolding.**[Citation Graph (0, 0)][DBLP] ICPP (1), 1989, pp:209-216 [Conf] - Rajiv Ramaswami, Keshab K. Parhi
**Distributed Scheduling of Broadcasts in a Radio Network.**[Citation Graph (0, 0)][DBLP] INFOCOM, 1989, pp:497-504 [Conf] - Bin Fu, Keshab K. Parhi
**Generalized Multiplication Free Arithmetic Codes.**[Citation Graph (0, 0)][DBLP] ISCAS, 1995, pp:437-440 [Conf] - Yongru Gu, Keshab K. Parhi
**Pipelining Tomlinson-Harashima precoders.**[Citation Graph (0, 0)][DBLP] ISCAS (1), 2005, pp:408-411 [Conf] - Chao Cheng, Keshab K. Parhi
**Hardware efficient fast parallel FIR filter structures based on iterated short convolution.**[Citation Graph (0, 0)][DBLP] ISCAS (3), 2004, pp:361-364 [Conf] - Chao Cheng, Keshab K. Parhi
**Further complexity reduction of parallel FIR filters.**[Citation Graph (0, 0)][DBLP] ISCAS (2), 2005, pp:1835-1838 [Conf] - Jin-Gyun Chung, Keshab K. Parhi
**The scaled normalized lattice digital filter.**[Citation Graph (0, 0)][DBLP] ISCAS, 1993, pp:483-486 [Conf] - Jin-Gyun Chung, Keshab K. Parhi
**Synthesis and Pipelining of Ladder Wave Digital Filters in Digital Domain.**[Citation Graph (0, 0)][DBLP] ISCAS, 1995, pp:77-80 [Conf] - Tracy C. Denk, Keshab K. Parhi
**Calculation of Minimum Number of Registers in 2-D Discrete Wavelet Transforms Using Lapped Block Processing.**[Citation Graph (0, 0)][DBLP] ISCAS, 1994, pp:77-80 [Conf] - Bin Fu, Keshab K. Parhi
**Two VLSI Design Advances in Arithmetic Coding.**[Citation Graph (0, 0)][DBLP] ISCAS, 1995, pp:1440-1443 [Conf] - Sang-Min Kim, Jun Tang, Keshab K. Parhi
**Quasi-cyclic low-density parity-check coded multi-band-OFDM UWB systems.**[Citation Graph (0, 0)][DBLP] ISCAS (1), 2005, pp:65-68 [Conf] - Jian-Hung Lin, Keshab K. Parhi
**VLSI architectures for stereoscopic video disparity matching and object extraction.**[Citation Graph (0, 0)][DBLP] ISCAS (3), 2005, pp:2373-2376 [Conf] - Keshab K. Parhi, Takao Nishitani
**Folded VLSI Architectures for Discrete Wavelet Transforms.**[Citation Graph (0, 0)][DBLP] ISCAS, 1993, pp:1734-1737 [Conf] - Ji-Suk Park, Byeong-Kuk Kim, Jin-Gyun Chung, Keshab K. Parhi
**High-speed tunable fractional-delay allpass filter structure.**[Citation Graph (0, 0)][DBLP] ISCAS (4), 2003, pp:165-168 [Conf] - Darren N. Pearson, Keshab K. Parhi
**Low-Power FIR Digital Filter Architectures.**[Citation Graph (0, 0)][DBLP] ISCAS, 1995, pp:231-234 [Conf] - Kalavai J. Raghunath, Keshab K. Parhi
**High Speed RLS Using Scaled Tangent Rotations (STAR).**[Citation Graph (0, 0)][DBLP] ISCAS, 1993, pp:1959-1962 [Conf] - Ebrahim Saberinia, Jun Tang, Ahmed H. Tewfik, Keshab K. Parhi
**Pulsed OFDM modulation for ultra wideband communications.**[Citation Graph (0, 0)][DBLP] ISCAS (5), 2004, pp:369-392 [Conf] - Naresh R. Shanbhag, Keshab K. Parhi
**Roundoff error analysis of the pipelined ADPCM coder.**[Citation Graph (0, 0)][DBLP] ISCAS, 1993, pp:886-889 [Conf] - Naresh R. Shanbhag, Keshab K. Parhi
**A Pipelined Adaptive Differential Vector Quantizer for Low-power Speech Coding Applications.**[Citation Graph (0, 0)][DBLP] ISCAS, 1993, pp:1956-1958 [Conf] - Hosahalli R. Srinivas, Keshab K. Parhi
**A Fast Radix-4 Division Algorithm.**[Citation Graph (0, 0)][DBLP] ISCAS, 1994, pp:311-314 [Conf] - Jun Tang, Ahmed H. Tewfik, Keshab K. Parhi
**High performance solution for interfering UWB piconets with reduced complexity sphere decoding.**[Citation Graph (0, 0)][DBLP] ISCAS (5), 2004, pp:377-380 [Conf] - Ching-Yi Wang, Keshab K. Parhi
**Loop List Scheduler for DSP Algorithms under Resource Consraints.**[Citation Graph (0, 0)][DBLP] ISCAS, 1993, pp:1662-1665 [Conf] - Imed Ben Dhaou, Hannu Tenhunen, Vijay Sundararajan, Keshab K. Parhi
**Energy efficient signaling in DSM CMOS technology.**[Citation Graph (0, 0)][DBLP] ISCAS (5), 2001, pp:411-414 [Conf] - Zhipei Chi, Leilei Song, Keshab K. Parhi
**A study on the performance, complexity tradeoffs of block turbo decoder design.**[Citation Graph (0, 0)][DBLP] ISCAS (4), 2001, pp:65-68 [Conf] - Lijun Gao, Keshab K. Parhi
**Custom VLSI design of efficient low latency and low power finite field multiplier for Reed-Solomon codec.**[Citation Graph (0, 0)][DBLP] ISCAS (4), 2001, pp:574-577 [Conf] - Tong Zhang, Zhongfeng Wang, Keshab K. Parhi
**On finite precision implementation of low density parity check codes decoder.**[Citation Graph (0, 0)][DBLP] ISCAS (4), 2001, pp:202-205 [Conf] - Leilei Song, Keshab K. Parhi
**Low-energy software Reed-Solomon codecs using specialized finite field datapath and division-free Berlekamp-Massey algorithm.**[Citation Graph (0, 0)][DBLP] ISCAS (1), 1999, pp:84-89 [Conf] - Leilei Song, Keshab K. Parhi
**Low-complexity modified Mastrovito multipliers over finite fields GF(2M).**[Citation Graph (0, 0)][DBLP] ISCAS (1), 1999, pp:508-512 [Conf] - William L. Freking, Keshab K. Parhi
**Parallel modular multiplication with application to VLSI RSA implementation.**[Citation Graph (0, 0)][DBLP] ISCAS (1), 1999, pp:490-495 [Conf] - S. Summerfield, Zhongfeng Wang, Keshab K. Parhi
**Area-power-time efficient pipeline-interleaved architectures for wave digital filters.**[Citation Graph (0, 0)][DBLP] ISCAS (3), 1999, pp:343-346 [Conf] - Zhipei Chi, Jun Ma, Keshab K. Parhi
**Pipelined QR decomposition based multi-channel least square lattice adaptive filter architectures.**[Citation Graph (0, 0)][DBLP] ISCAS (3), 1999, pp:49-53 [Conf] - Jun Ma, Keshab K. Parhi, Ed F. Deprettere
**Derivation of parallel and pipelined orthogonal filter architectures via algorithm transformations.**[Citation Graph (0, 0)][DBLP] ISCAS (3), 1999, pp:347-350 [Conf] - A. F. Shalash, Keshab K. Parhi
**Multiple access over wireline channels using orthogonal signaling.**[Citation Graph (0, 0)][DBLP] ISCAS (4), 1999, pp:580-583 [Conf] - Yuping Zhang, Keshab K. Parhi
**Parallel Turbo decoding.**[Citation Graph (0, 0)][DBLP] ISCAS (2), 2004, pp:509-512 [Conf] - Keshab K. Parhi
**Novel pipelining of MSB-first add-compare select unit structure for Viterbi decoders.**[Citation Graph (0, 0)][DBLP] ISCAS (2), 2004, pp:501-504 [Conf] - Zhipei Chi, Keshab K. Parhi
**High speed VLSI architecture design for block turbo decoder.**[Citation Graph (0, 0)][DBLP] ISCAS (1), 2002, pp:901-904 [Conf] - Gunok Jung, Jun Jin Kong, Gerald E. Sobelman, Keshab K. Parhi
**High-speed add-compare-select units using locally self-resetting CMOS.**[Citation Graph (0, 0)][DBLP] ISCAS (1), 2002, pp:889-892 [Conf] - Sang-Min Kim, Jin-Gyun Chung, Keshab K. Parhi
**Design of low error CSD fixed-width multiplier.**[Citation Graph (0, 0)][DBLP] ISCAS (1), 2002, pp:69-72 [Conf] - Vijay Sundararajan, Keshab K. Parhi
**Low power synthesis of dual threshold voltage CMOS VLSI circuits.**[Citation Graph (0, 0)][DBLP] ISLPED, 1999, pp:139-144 [Conf] - Imed Ben Dhaou, Hannu Tenhunen, Vijay Sundararajan, Keshab K. Parhi
**Energy Efficient Signaling in Deep Submicron CMOS Technology.**[Citation Graph (0, 0)][DBLP] ISQED, 2001, pp:319-324 [Conf] - Gireesh Shrimali, Keshab K. Parhi
**High-Speed Arithmetic Coder/Decoder Architectures.**[Citation Graph (0, 0)][DBLP] PPSC, 1993, pp:1025-1032 [Conf] - W. Amendola Jr., Hosahalli R. Srinivas, Keshab K. Parhi
**A 16-bit x 16-bit 1.2 /spl mu/ CMOS multiplier with low latency vector merging.**[Citation Graph (0, 0)][DBLP] VLSI Design, 1995, pp:398-402 [Conf] - Keshab K. Parhi
**Calculation of Minimum Number of Registers in Arbitrary Life Time Chart.**[Citation Graph (0, 0)][DBLP] VLSI Design, 1994, pp:83-86 [Conf] - Janardhan H. Satyanarayana, Keshab K. Parhi
**Power Estimation of Digital Data Paths Using HEAT.**[Citation Graph (0, 0)][DBLP] IEEE Design & Test of Computers, 2000, v:17, n:2, pp:101-110 [Journal] - Michael E. Zervakis, Vijay Sundararajan, Keshab K. Parhi
**Vector processing of wavelet coefficients for robust image denoising.**[Citation Graph (0, 0)][DBLP] Image Vision Comput., 2001, v:19, n:7, pp:435-450 [Journal] - Luis A. Montalvo, Keshab K. Parhi, Alain Guyot
**New Svoboda-Tung Division.**[Citation Graph (0, 0)][DBLP] IEEE Trans. Computers, 1998, v:47, n:9, pp:1014-1020 [Journal] - Keshab K. Parhi, David G. Messerschmitt
**Static Rate-Optimal Scheduling of Iterative Data-Flow Programs via Optimum Unfolding.**[Citation Graph (0, 0)][DBLP] IEEE Trans. Computers, 1991, v:40, n:2, pp:178-195 [Journal] - Keshab K. Parhi, Frank H. Wu, Kalyan Genesan
**Sequential and Parallel Neural Network Vector Quantizers.**[Citation Graph (0, 0)][DBLP] IEEE Trans. Computers, 1994, v:43, n:1, pp:104-109 [Journal] - Hosahalli R. Srinivas, Keshab K. Parhi
**A Fast Radix-4 Division Algorithm and Its Architecture.**[Citation Graph (0, 0)][DBLP] IEEE Trans. Computers, 1995, v:44, n:6, pp:826-831 [Journal] - Hosahalli R. Srinivas, Keshab K. Parhi, Luis A. Montalvo
**Radix 2 Division with Over-Redundant Quotient Selection.**[Citation Graph (0, 0)][DBLP] IEEE Trans. Computers, 1997, v:46, n:1, pp:85-92 [Journal] - Tong Zhang, Keshab K. Parhi
**Systematic Design of Original and Modified Mastrovito Multipliers for General Irreducible Polynomials.**[Citation Graph (0, 0)][DBLP] IEEE Trans. Computers, 2001, v:50, n:7, pp:734-749 [Journal] - Lori E. Lucke, Keshab K. Parhi
**Data-flow transformations for critical path time reduction in high-level DSP synthesis.**[Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:7, pp:1063-1068 [Journal] - Vijay Sundararajan, Sachin S. Sapatnekar, Keshab K. Parhi
**Fast and exact transistor sizing based on iterative relaxation.**[Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:5, pp:568-581 [Journal] - Ching-Yi Wang, Keshab K. Parhi
**High-level DSP synthesis using concurrent transformations, scheduling, and allocation.**[Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:3, pp:274-295 [Journal] - Zhipei Chi, Leilei Song, Keshab K. Parhi
**On The Performance/Complexity Tradeoff in Block Turbo Decoder Design.**[Citation Graph (0, 0)][DBLP] IEEE Transactions on Communications, 2004, v:52, n:2, pp:173-175 [Journal] - Zhipei Chi, Zhongfeng Wang, Keshab K. Parhi
**On the better protection of short-frame turbo codes.**[Citation Graph (0, 0)][DBLP] IEEE Transactions on Communications, 2004, v:52, n:9, pp:1435-1439 [Journal] - Vijay Sundararajan, Sachin S. Sapatnekar, Keshab K. Parhi
**A new approach for integration of min-area retiming and min-delay padding for simultaneously addressing short-path and long-path constraints.**[Citation Graph (0, 0)][DBLP] ACM Trans. Design Autom. Electr. Syst., 2004, v:9, n:3, pp:273-289 [Journal] - Yanni Chen, Keshab K. Parhi
**Small area parallel Chien search architectures for long BCH codes.**[Citation Graph (0, 0)][DBLP] IEEE Trans. VLSI Syst., 2004, v:12, n:5, pp:545-549 [Journal] - Kyung-Ju Cho, Kwang-Chul Lee, Jin-Gyun Chung, Keshab K. Parhi
**Design of low-error fixed-width modified booth multiplier.**[Citation Graph (0, 0)][DBLP] IEEE Trans. VLSI Syst., 2004, v:12, n:5, pp:522-531 [Journal] - Keshab K. Parhi
**Design of multigigabit multiplexer-loop-based decision feedback equalizers.**[Citation Graph (0, 0)][DBLP] IEEE Trans. VLSI Syst., 2005, v:13, n:4, pp:489-493 [Journal] - Jun Jin Kong, Keshab K. Parhi
**Low-latency architectures for high-throughput rate Viterbi decoders.**[Citation Graph (0, 0)][DBLP] IEEE Trans. VLSI Syst., 2004, v:12, n:6, pp:642-651 [Journal] - Xinmiao Zhang, Keshab K. Parhi
**High-speed VLSI architectures for the AES algorithm.**[Citation Graph (0, 0)][DBLP] IEEE Trans. VLSI Syst., 2004, v:12, n:9, pp:957-967 [Journal] - Xinmiao Zhang, Keshab K. Parhi
**Fast factorization architecture in soft-decision Reed-Solomon decoding.**[Citation Graph (0, 0)][DBLP] IEEE Trans. VLSI Syst., 2005, v:13, n:4, pp:413-426 [Journal] - Xinmiao Zhang, Keshab K. Parhi
**High-Speed Architectures for Parallel Long BCH Encoders.**[Citation Graph (0, 0)][DBLP] IEEE Trans. VLSI Syst., 2005, v:13, n:7, pp:872-877 [Journal] - Yuping Zhang, Keshab K. Parhi
**Parallel Architecture of List Sphere Decoders.**[Citation Graph (0, 0)][DBLP] ISCAS, 2007, pp:2096-2099 [Conf] - Daesun Oh, Keshab K. Parhi
**Efficient Highly-Parallel Decoder Architecture for Quasi-Cyclic Low-Density Parity-Check Codes.**[Citation Graph (0, 0)][DBLP] ISCAS, 2007, pp:1855-1858 [Conf] - Daesun Oh, Keshab K. Parhi
**Performance of Quantized Min-Sum Decoding Algorithms for Irregular LDPC Codes.**[Citation Graph (0, 0)][DBLP] ISCAS, 2007, pp:2758-2761 [Conf] - Aaron E. Cohen, Keshab K. Parhi
**Faster elliptic curve point multiplication based on a novel greedy base-2, 3 method.**[Citation Graph (0, 0)][DBLP] ISCAS, 2006, pp:- [Conf] - Jian-Hung Lin, Keshab K. Parhi
**Low complexity block turbo equalization.**[Citation Graph (0, 0)][DBLP] ISCAS, 2006, pp:- [Conf] - Keshab K. Parhi, Takao Nishitani
**VLSI architectures for discrete wavelet transforms.**[Citation Graph (0, 0)][DBLP] IEEE Trans. VLSI Syst., 1993, v:1, n:2, pp:191-202 [Journal] - Hosahalli R. Srinivas, Bapiraju Vinnakota, Keshab K. Parhi
**A C-testable carry-free divider.**[Citation Graph (0, 0)][DBLP] IEEE Trans. VLSI Syst., 1994, v:2, n:4, pp:472-488 [Journal] - Tracy C. Denk, Keshab K. Parhi
**Synthesis of folded pipelined architectures for multirate DSP algorithms.**[Citation Graph (0, 0)][DBLP] IEEE Trans. VLSI Syst., 1998, v:6, n:4, pp:595-607 [Journal] - S. K. Jain, Leilei Song, Keshab K. Parhi
**Efficient semisystolic architectures for finite-field arithmetic.**[Citation Graph (0, 0)][DBLP] IEEE Trans. VLSI Syst., 1998, v:6, n:1, pp:101-113 [Journal] - K. Ito, Lori E. Lucke, Keshab K. Parhi
**ILP-based cost-optimal DSP synthesis with module selection and data format conversion.**[Citation Graph (0, 0)][DBLP] IEEE Trans. VLSI Syst., 1998, v:6, n:4, pp:582-594 [Journal] - Keshab K. Parhi
**Low-energy CSMT carry generators and binary adders.**[Citation Graph (0, 0)][DBLP] IEEE Trans. VLSI Syst., 1999, v:7, n:4, pp:450-462 [Journal] - Tracy C. Denk, Keshab K. Parhi
**Two-dimensional retiming [VLSI design].**[Citation Graph (0, 0)][DBLP] IEEE Trans. VLSI Syst., 1999, v:7, n:2, pp:198-211 [Journal] - Leilei Song, Keshab K. Parhi, I. Kuroda, T. Nishitani
**Hardware/software codesign of finite field datapath for low-energy Reed-Solomon codecs.**[Citation Graph (0, 0)][DBLP] IEEE Trans. VLSI Syst., 2000, v:8, n:2, pp:160-172 [Journal] - Janardhan H. Satyanarayana, Keshab K. Parhi
**Theoretical analysis of word-level switching activity in the presence of glitching and correlation.**[Citation Graph (0, 0)][DBLP] IEEE Trans. VLSI Syst., 2000, v:8, n:2, pp:148-159 [Journal] - Zhongfeng Wang, Zhipei Chi, Keshab K. Parhi
**Area-efficient high-speed decoding schemes for turbo decoders.**[Citation Graph (0, 0)][DBLP] IEEE Trans. VLSI Syst., 2002, v:10, n:6, pp:902-912 [Journal] - Yongru Gu, Keshab K. Parhi
**Interleaved Trellis Coded Modulation and Decoder Optimizations for 10 Gigabit Ethernet over Copper.**[Citation Graph (0, 0)][DBLP] VLSI Signal Processing, 2006, v:42, n:3, pp:211-221 [Journal] - Chao Cheng, Keshab K. Parhi
**Hardware Efficient Fast Computation of the Discrete Fourier Transform.**[Citation Graph (0, 0)][DBLP] VLSI Signal Processing, 2006, v:42, n:2, pp:159-171 [Journal] - Chao Cheng, Keshab K. Parhi
**Hardware efficient fast computation of the discrete fourier transform.**[Citation Graph (0, 0)][DBLP] VLSI Signal Processing, 2006, v:43, n:1, pp:105-106 [Journal] - Lijun Gao, Keshab K. Parhi
**Models for Architectural Power and Power Grid Noise Analysis on Data Bus.**[Citation Graph (0, 0)][DBLP] VLSI Signal Processing, 2006, v:44, n:1-2, pp:25-46 [Journal] **Nonuniformly quantized min-sum decoder architecture for low-density parity-check codes.**[Citation Graph (, )][DBLP]**Fast composite field S-box architectures for advanced encryption standard.**[Citation Graph (, )][DBLP]**Area efficient controller design of barrel shifters for reconfigurable LDPC decoders.**[Citation Graph (, )][DBLP]**Variable Length Teager Energy Based Mel Cepstral Features for Identification of Twins.**[Citation Graph (, )][DBLP]**Further cost reduction of adaptive echo and next cancellers for high-speed Ethernet transceivers.**[Citation Graph (, )][DBLP]**Minimal complexity low-latency architectures for Viterbi decoders.**[Citation Graph (, )][DBLP]**Low Complexity List Updating Circuits for List Sphere Decoders.**[Citation Graph (, )][DBLP]**Low Complexity Implementations of Sum-Product Algorithm for Decoding Low-Density Parity-Check Codes.**[Citation Graph (, )][DBLP]**Adaptive Tap Management in Multi-Gigabit Echo & Next Cancellers.**[Citation Graph (, )][DBLP]**Low complexity iterative joint detection, decoding, and channel estimation for wireless MIMO system.**[Citation Graph (, )][DBLP]**Sparse severe error removal in OFDM demodulators for erasure channels.**[Citation Graph (, )][DBLP]
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