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Cheng-Kok Koh: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Yongxin Zhu, Weng-Fai Wong, Cheng-Kok Koh
    A Performance and Power Co-optimization Approach for Modern Processors. [Citation Graph (0, 0)][DBLP]
    CIT, 2005, pp:822-828 [Conf]
  2. Aiqun Cao, Ruibing Lu, Cheng-Kok Koh
    Post-layout logic duplication for synthesis of domino circuits with complex gates. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:260-265 [Conf]
  3. Yiran Chen, Kaushik Roy, Cheng-Kok Koh
    Priority assignment optimization for minimization of current surge in high performance power efficient clock-gated microprocessor. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:893-898 [Conf]
  4. Jitesh Jain, Stephen Cauley, Cheng-Kok Koh, Venkataramanan Balakrishnan
    SASIMI: sparsity-aware simulation of interconnect-dominated circuits with non-linear devices. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:422-427 [Conf]
  5. Wai-Ching Douglas Lam, Cheng-Kok Koh
    Process variation robust clock tree routing. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:606-611 [Conf]
  6. Hong Li, Venkataramanan Balakrishnan, Cheng-Kok Koh, Guoan Zhong
    Compact and stable modeling of partial inductance and reluctance matrices. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:507-510 [Conf]
  7. Hai Li, Yiran Chen, Kaushik Roy, Cheng-Kok Koh
    SAVS: a self-adaptive variable supply-voltage technique for process- tolerant and power-efficient multi-issue superscalar processor design. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:158-163 [Conf]
  8. Chen Li 0004, Cheng-Kok Koh, Patrick H. Madden
    Floorplan management: incremental placement for gate sizing and buffer insertion. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:349-354 [Conf]
  9. Ruibing Lu, Aiqun Cao, Cheng-Kok Koh
    Improving the scalability of SAMBA bus architecture. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:1164-1167 [Conf]
  10. Ruibing Lu, Cheng-Kok Koh
    A high performance bus communication architecture through bus splitting. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:751-755 [Conf]
  11. Q. Su, Venkataramanan Balakrishnan, Cheng-Kok Koh
    Efficient Approximate Balanced Truncation of General Large-Scale RLC Systems via Krylov Methods. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2002, pp:311-316 [Conf]
  12. Ya-Chi Yang, Cheng-Kok Koh, Venkataramanan Balakrishnan
    Adaptive admittance-based conductor meshing for interconnect analysis. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:509-514 [Conf]
  13. Shiyou Zhao, Kaushik Oy, Cheng-Kok Koh
    Power Supply Noise Aware Floorplanning and Decoupling Capacitance Placement. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2002, pp:489-498 [Conf]
  14. Aiqun Cao, Cheng-Kok Koh
    Post-layout logic optimization of domino circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:820-825 [Conf]
  15. Q. Su, Venkataramanan Balakrishnan, Cheng-Kok Koh
    A factorization-based framework for passivity-preserving model reduction of RLC systems. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:40-45 [Conf]
  16. Ngai Wong, Venkataramanan Balakrishnan, Cheng-Kok Koh
    Passivity-preserving model reduction via a computationally efficient project-and-balance scheme. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:369-374 [Conf]
  17. Rongtian Zhang, Kaushik Roy, Cheng-Kok Koh, David B. Janes
    Exploring SOI Device Structures and Interconnect Architectures for 3-Dimensional Integration. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:846-851 [Conf]
  18. Guoan Zhong, Cheng-Kok Koh, Venkataramanan Balakrishnan, Kaushik Roy
    An adaptive window-based susceptance extraction and its efficient implementation. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:728-731 [Conf]
  19. Ruibing Lu, Cheng-Kok Koh
    Interconnect Planning with Local Area Constrained Retiming. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10442-10447 [Conf]
  20. Yiran Chen, Venkataramanan Balakrishnan, Cheng-Kok Koh, Kaushik Roy
    Model Reduction in the Time-Domain Using Laguerre Polynomials and Krylov Methods. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:931-937 [Conf]
  21. Ruibing Lu, Guoan Zhong, Cheng-Kok Koh, Kai-Yuan Chao
    Flip-Flop and Repeater Insertion for Early Interconnect Planning. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:690-695 [Conf]
  22. Probir Sarkar, Cheng-Kok Koh
    Repeater block planning under simultaneous delay and transition time constraints. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:540-545 [Conf]
  23. Cheng-Kok Koh, Patrick H. Madden
    Manhattan or non-Manhattan?: a study of alternative VLSI routing architectures. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2000, pp:47-52 [Conf]
  24. Jacob R. Minz, Sung Kyu Lim, Cheng-Kok Koh
    3D module placement for congestion and power noise reduction. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2005, pp:458-461 [Conf]
  25. Jason Cong, Lei He, Cheng-Kok Koh, David Zhigang Pan
    Global interconnect sizing and spacing with consideration of coupling capacitance. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1997, pp:628-633 [Conf]
  26. Jason Cong, Cheng-Kok Koh
    Simultaneous driver and wire sizing for performance and power optimization. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1994, pp:206-212 [Conf]
  27. Jason Cong, Cheng-Kok Koh
    Interconnect layout optimization under higher-order RLC model. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1997, pp:713-720 [Conf]
  28. Jason Cong, Andrew B. Kahng, Cheng-Kok Koh, Chung-Wen Albert Tsao
    Bounded-skew clock and Steiner routing under Elmore delay. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1995, pp:66-71 [Conf]
  29. Jason Cong, David Zhigang Pan, Lei He, Cheng-Kok Koh, Kei-Yong Khoo
    Interconnect design for deep submicron ICs. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1997, pp:478-485 [Conf]
  30. Jitesh Jain, Cheng-Kok Koh, Venkataramanan Balakrishnan
    Fast simulation of VLSI interconnects. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2004, pp:93-98 [Conf]
  31. Ruibing Lu, Cheng-Kok Koh
    Performance Optimization of Latency Insensitive Systems Through Buffer Queue Sizing of Communication Channels. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2003, pp:227-231 [Conf]
  32. Ruibing Lu, Cheng-Kok Koh
    SAMBA-Bus: A High Performance Bus Architecture for System-on-Chips. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2003, pp:8-12 [Conf]
  33. Chen Li 0004, Min Xie, Cheng-Kok Koh, Jason Cong, Patrick H. Madden
    Routability-driven placement and white space allocation. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2004, pp:394-401 [Conf]
  34. Wai-Ching Douglas Lam, J. Jam, Cheng-Kok Koh, Venkataramanan Balakrishnan, Yiran Chen
    Statistical based link insertion for robust clock network design. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2005, pp:588-591 [Conf]
  35. Chung-Wen Albert Tsao, Cheng-Kok Koh
    UST/DME: A Clock Tree Router for General Skew Constraints. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2000, pp:400-405 [Conf]
  36. Rongtian Zhang, Kaushik Roy, Cheng-Kok Koh, David B. Janes
    Stochastic Wire-Length and Delay Distribution of 3-Dimensional Circuits. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2000, pp:208-213 [Conf]
  37. Shiyou Zhao, Kaushik Roy, Cheng-Kok Koh
    Frequency Domain Analysis of Switching Noise on Power Supply Network. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2000, pp:487-492 [Conf]
  38. Guoan Zhong, Cheng-Kok Koh, Kaushik Roy
    A Twisted Bundle Layout Structure for Minimizing Inductive Coupling Noise. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2000, pp:406-411 [Conf]
  39. Guoan Zhong, Cheng-Kok Koh, Kaushik Roy
    On-chip interconnect modeling by wire duplication. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2002, pp:341-346 [Conf]
  40. Hong Li, Venkataramanan Balakrishnan, Cheng-Kok Koh
    Stable and compact inductance modeling of 3-D interconnect structures. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2006, pp:1-6 [Conf]
  41. Aiqun Cao, Cheng-Kok Koh
    Non-Crossing OBDDs for Mapping to Regular Circuit Structures. [Citation Graph (0, 0)][DBLP]
    ICCD, 2003, pp:338-343 [Conf]
  42. Alexandre Solomatnikov, Kaushik Roy, Cheng-Kok Koh, Dinesh Somasekhar
    Skewed CMOS: Noise-Immune High-Performance Low-Power Static Circuit Family. [Citation Graph (0, 0)][DBLP]
    ICCD, 2000, pp:241-246 [Conf]
  43. Shiyou Zhao, Kaushik Roy, Cheng-Kok Koh
    Estimation of Inductive and Resistive Switching Noise on Power Supply Network in Deep Sub-Micron CMOS Circuits. [Citation Graph (0, 0)][DBLP]
    ICCD, 2000, pp:65-72 [Conf]
  44. Guoan Zhong, Cheng-Kok Koh
    Exact Closed Form Formula for Partial Mutual Inductances of On-Chip Interconnects. [Citation Graph (0, 0)][DBLP]
    ICCD, 2002, pp:428-433 [Conf]
  45. Jason Cong, Cheng-Kok Koh
    Minimum-Cost Bounded-Skew Clock Routing. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1995, pp:215-218 [Conf]
  46. Rongtian Zhang, Kaushik Roy, Cheng-Kok Koh, David B. Janes
    Power trends and performance characterization of 3-dimensional integration. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:414-417 [Conf]
  47. Rui Wang, Kaushik Roy, Cheng-Kok Koh
    Short-circuit power analysis of an inverter driving an RLC load. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:886-889 [Conf]
  48. Yiran Chen, Hai Li, Kaushik Roy, Cheng-Kok Koh
    Cascaded carry-select adder (C2SA): a new structure for low-power CSA design. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2005, pp:115-118 [Conf]
  49. Yiran Chen, Kaushik Roy, Cheng-Kok Koh
    Integrated architectural/physical planning approach for minimization of current surge in high performance clock-gated microprocessors. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2003, pp:229-234 [Conf]
  50. Jason Cong, Cheng-Kok Koh, Kwok-Shing Leung
    Simultaneous buffer and wire sizing for performance and power optimization. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1996, pp:271-276 [Conf]
  51. Naran Sirisantana, Aiqun Cao, Shawn Davidson, Cheng-Kok Koh, Kaushik Roy
    Selectively clocked skewed logic (SCSL): low-power logic style for high-performance applications. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2001, pp:267-270 [Conf]
  52. Ateen Khatkhate, Chen Li 0004, Ameya R. Agnihotri, Mehmet Can Yildiz, Satoshi Ono, Cheng-Kok Koh, Patrick H. Madden
    Recursive bisection based mixed block placement. [Citation Graph (0, 0)][DBLP]
    ISPD, 2004, pp:84-89 [Conf]
  53. Probir Sarkar, Vivek Sundararaman, Cheng-Kok Koh
    Routability-driven repeater block planning for interconnect-centric floorplanning. [Citation Graph (0, 0)][DBLP]
    ISPD, 2000, pp:186-191 [Conf]
  54. Shiyou Zhao, Kaushik Roy, Cheng-Kok Koh
    Decoupling capacitance allocation for power supply noise suppression. [Citation Graph (0, 0)][DBLP]
    ISPD, 2001, pp:66-71 [Conf]
  55. Aiqun Cao, Naran Sirisantana, Cheng-Kok Koh, Kaushik Roy
    Synthesis of Selectively Clocked Skewed Logic Circuits. [Citation Graph (0, 0)][DBLP]
    ISQED, 2002, pp:229-234 [Conf]
  56. Wai-Ching Douglas Lam, Cheng-Kok Koh, Chung-Wen Albert Tsao
    Power Supply Noise Suppression via Clock Skew Scheduling. [Citation Graph (0, 0)][DBLP]
    ISQED, 2002, pp:355-360 [Conf]
  57. Wai-Ching Douglas Lam, Cheng-Kok Koh, Chung-Wen Albert Tsao
    Clock Scheduling for Power Supply Noise Suppression using Genetic Algorithm with Selective Gene Therapy. [Citation Graph (0, 0)][DBLP]
    ISQED, 2003, pp:327-332 [Conf]
  58. Chen Li 0004, Cheng-Kok Koh
    Recursive Function Smoothing of Half-Perimeter Wirelength for Analytical Placement. [Citation Graph (0, 0)][DBLP]
    ISQED, 2007, pp:829-834 [Conf]
  59. Hong Li, Jitesh Jain, Venkataramanan Balakrishnan, Cheng-Kok Koh
    Efficient Analysis of Large-Scale Power Grids Based on a Compact Cholesky Factorization. [Citation Graph (0, 0)][DBLP]
    ISQED, 2007, pp:627-632 [Conf]
  60. Rongtian Zhang, Kaushik Roy, Cheng-Kok Koh, David B. Janes
    Power Trends and Performance Characterization of 3-Dimensional Integration for Future Technology Generations. [Citation Graph (0, 0)][DBLP]
    ISQED, 2001, pp:217-222 [Conf]
  61. Hong Li, Cheng-Kok Koh, Venkataramanan Balakrishnan, Yiran Chen
    Statistical Timing Analysis Considering Spatial Correlations. [Citation Graph (0, 0)][DBLP]
    ISQED, 2007, pp:102-107 [Conf]
  62. Q. Su, Venkataramanan Balakrishnan, Cheng-Kok Koh
    Efficient Approximate Balanced Truncation of General Large-Scale RLC Systems via Krylov Methods. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:311-316 [Conf]
  63. Shiyou Zhao, Kaushik Roy, Cheng-Kok Koh
    Power Supply Noise Aware Floorplanning and Decoupling Capacitance Placement. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:489-0 [Conf]
  64. Jason Cong, Lei He, Cheng-Kok Koh, Patrick H. Madden
    Performance optimization of VLSI interconnect layout. [Citation Graph (0, 0)][DBLP]
    Integration, 1996, v:21, n:1-2, pp:1-94 [Journal]
  65. Ameya R. Agnihotri, Satoshi Ono, Chen Li 0004, Mehmet Can Yildiz, Ateen Khatkhate, Cheng-Kok Koh, Patrick H. Madden
    Mixed block placement via fractional cut recursive bisection. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:5, pp:748-761 [Journal]
  66. Jason Cong, Lei He, Cheng-Kok Koh, David Zhigang Pan
    Interconnect sizing and spacing with consideration of couplingcapacitance. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:9, pp:1164-1169 [Journal]
  67. Jason Cong, Cheng-Kok Koh, Patrick H. Madden
    Interconnect layout optimization under higher order RLC model forMCM designs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:12, pp:1455-1463 [Journal]
  68. Ruibing Lu, Cheng-Kok Koh
    Performance analysis of latency-insensitive systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:3, pp:469-483 [Journal]
  69. Probir Sarkar, Cheng-Kok Koh
    Routability-driven repeater block planning for interconnect-centricfloorplanning. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:5, pp:660-671 [Journal]
  70. Shiyou Zhao, Kaushik Roy, Cheng-Kok Koh
    Decoupling capacitance allocation and its application topower-supply noise-aware floorplanning. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:1, pp:81-92 [Journal]
  71. Guoan Zhong, Cheng-Kok Koh, Kaushik Roy
    On-chip interconnect modeling by wire duplication. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:11, pp:1521-1532 [Journal]
  72. Aiqun Cao, Naran Sirisantana, Cheng-Kok Koh, Kaushik Roy
    Synthesis of skewed logic circuits. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2005, v:10, n:2, pp:205-228 [Journal]
  73. Jason Cong, Andrew B. Kahng, Cheng-Kok Koh, Chung-Wen Albert Tsao
    Bounded-skew clock and Steiner routing. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 1998, v:3, n:3, pp:341-388 [Journal]
  74. Chung-Wen Albert Tsao, Cheng-Kok Koh
    UST/DME: a clock tree router for general skew constraints. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2002, v:7, n:3, pp:359-379 [Journal]
  75. Aiqun Cao, Ruibing Lu, Chen Li 0004, Cheng-Kok Koh
    Postlayout optimization for synthesis of Domino circuits. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2006, v:11, n:4, pp:797-821 [Journal]
  76. Yiran Chen, Kaushik Roy, Cheng-Kok Koh
    Current demand balancing: a technique for minimization of current surge in high performance clock-gated microprocessors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:1, pp:75-85 [Journal]
  77. Ruibing Lu, Aiqun Cao, Cheng-Kok Koh
    SAMBA-Bus: A High Performance Bus Architecture for System-on-Chips. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:1, pp:69-79 [Journal]
  78. Jason Cong, Cheng-Kok Koh
    Simultaneous driver and wire sizing for performance and power optimization. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1994, v:2, n:4, pp:408-425 [Journal]

  79. A direct integral-equation solver of linear complexity for large-scale 3D capacitance and impedance extraction. [Citation Graph (, )][DBLP]


  80. A fast band-matching technique for interconnect inductance modeling. [Citation Graph (, )][DBLP]


  81. A frequency-domain technique for statistical timing analysis of clock meshes. [Citation Graph (, )][DBLP]


  82. Guiding global placement with wire density. [Citation Graph (, )][DBLP]


  83. A study of routability estimation and clustering in placement. [Citation Graph (, )][DBLP]


  84. VOSCH: Voltage scaled cache hierarchies. [Citation Graph (, )][DBLP]


  85. A fast band matching technique for impedance extraction. [Citation Graph (, )][DBLP]


  86. Variable-latency adder (VL-adder): new arithmetic circuit design practice to overcome NBTI. [Citation Graph (, )][DBLP]


  87. Optimal post-routing redundant via insertion. [Citation Graph (, )][DBLP]


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